FB1
FB2
FB3
FB4
FB5
FB6
FB7
FB8
Signal Name
Total Product Terms
Product Terms
Location
Power Mode
Pin Number
PinType
Pin Use
(unused)
0
MC1
(b)
(b)
ram_rom_adr<12>
22
18_4
18_5
1_1
1_2
1_3
1_4
1_5
2_1
2_2
2_3
2_4
2_5
3_1
3_2
3_3
3_4
3_5
4_1
4_2
4_3
4_4
4_5
MC2
LOW
35
I/O
O
(unused)
0
MC3
(b)
(b)
i2c_clk_and0000/i2c_clk_and0000_D2
1
5_2
MC4
LOW
(b)
(b)
data_0_cmp_eq0002/data_0_cmp_eq0002_D2
1
5_1
MC5
LOW
36
I/O
I
turbo_centronics_clk__or0001/turbo_centronics_clk__or0001_D2
2
6_1
6_2
MC6
LOW
37
I/O
I
ram_bank_5
2
7_1
7_2
MC7
LOW
(b)
(b)
data_0_or0000/data_0_or0000_D2
2
8_1
8_2
MC8
LOW
39
I/O
I
$OpTx$FX_DC$475
2
9_1
9_2
MC9
LOW
40
I/O
I
$OpTx$FX_DC$461
2
10_1
9_3
MC10
LOW
(b)
(b)
rom_ce
9
10_2
10_3
10_4
10_5
11_1
11_2
11_3
11_4
11_5
MC11
LOW
41
I/O
O
ram_ce
14
12_1
12_2
12_3
12_4
12_5
13_1
13_2
13_3
13_4
13_5
14_2
14_3
14_4
14_5
MC12
LOW
42
I/O
O
(unused)
0
MC13
(b)
(b)
i2c_clk
3
14_1
15_4
15_5
MC14
LOW
43
I/O
I
happy_a12
3
15_1
15_2
15_3
MC15
LOW
46
I/O
I
data_7_or0005/data_7_or0005_D2
5
16_1
16_2
16_3
16_4
16_5
MC16
LOW
(b)
(b)
ram_rom_oe
1
17_1
MC17
LOW
49
I/O
O
$OpTx$FX_DC$556
5
17_2
17_3
18_1
18_2
18_3
MC18
LOW
(b)
(b)
Signals Used By Logic in Function Block
$OpTx$FX_DC$475
$OpTx$FX_DC$501
$OpTx$FX_DC$502
$OpTx$FX_DC$515
$OpTx$FX_DC$556
$OpTx$FX_SC$508
N104/N104_D2
data<5>.PIN
N27/N27_D2
adr<0>
adr<10>
adr<11>
adr<12>
adr<13>
adr<14>
adr<15>
adr<1>
adr<2>
adr<3>
adr<4>
adr<5>
adr<6>
adr<7>
adr<8>
adr<9>
check_1050_6810_access_cmp_eq0000/check_1050_6810_access_cmp_eq0000_D2
floppy_mode<0>
floppy_mode<1>
floppy_mode<2>
floppy_mode<3>
happy_a12
happy_a12__or0001/happy_a12__or0001_D2
i2c_clk
i2c_clk_and0000/i2c_clk_and0000_D2
phi2
ram_bank_3
ram_bank_4
ram_bank_5
reset
rom_bank_c000_enable<0>
rom_base_bank_0
rom_source_is_ram
rw
turbo_rom_adr<12>