Signal Name Total Product Terms Product Terms Location Power Mode Pin Number PinType Pin Use
(unused) 0   MC1     (b)  
turbo_rom_adr_11__or0001/turbo_rom_adr_11__or0001_D2 2  2_1 2_2 MC2 LOW 23 I/O/GCK2 I
rom_base_bank_5 2  3_1 3_2 MC3 LOW   (b) (b)
rom_base_bank_4 2  4_1 4_2 MC4 LOW   (b) (b)
ram_rom_adr<10> 3  5_1 5_2 5_3 MC5 LOW 24 I/O O
rom_base_bank_3 2  6_1 6_2 MC6 LOW 25 I/O I
rom_base_bank_2 2  7_1 7_2 MC7 LOW   (b) (b)
rom_bank_c000_5 2  8_1 8_2 MC8 LOW 27 I/O/GCK3 GCK/I
rom_bank_c000_4 2  9_1 9_2 MC9 LOW 28 I/O I
rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2 2  10_1 10_2 MC10 LOW   (b) (b)
ram_bank_4 2  11_1 11_2 MC11 LOW 29 I/O I
ram_bank_3 2  12_1 12_2 MC12 LOW 30 I/O I
ram_bank_2 2  13_1 13_2 MC13 LOW   (b) (b)
ram_bank_1 2  14_1 14_2 MC14 LOW 32 I/O I
ram_rom_adr<11> 9  14_3 14_4 15_1 15_2 15_3 15_4 15_5 16_3 16_4 MC15 LOW 33 I/O O
ram_bank_0 2  16_1 16_2 MC16 LOW   (b) (b)
riot_ready_inout 2  17_1 17_2 MC17 LOW 34 I/O I/O
i2c_data 3  18_1 18_2 18_3 MC18 LOW   (b) (b)

Signals Used By Logic in Function Block
  1. $OpTx$FX_DC$475
  2. $OpTx$FX_DC$515
  3. $OpTx$FX_SC$520
  4. N104/N104_D2
  5. d7_ram_rom.PIN
  6. data<5>.PIN
  7. data<4>.PIN
  8. data<3>.PIN
  9. data<2>.PIN
  10. data<1>.PIN
  11. data<0>.PIN
  12. N27/N27_D2
  13. adr<10>
  14. adr<11>
  15. adr<12>
  16. adr<1>
  17. adr<7>
  18. archiver_a11
  19. check_1050_6810_access_cmp_eq0000/check_1050_6810_access_cmp_eq0000_D2
  20. data_0_cmp_eq0001/data_0_cmp_eq0001_D2
  21. floppy_mode<0>
  22. floppy_mode<1>
  23. floppy_mode<2>
  24. floppy_mode<3>
  25. i2c_clk_and0000/i2c_clk_and0000_D2
  26. i2c_data
  27. ram_bank_0
  28. ram_bank_1
  29. ram_bank_2
  30. ram_bank_3
  31. ram_bank_4
  32. reset
  33. riot_ready_in
  34. rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2
  35. rom_bank_c000_4
  36. rom_bank_c000_5
  37. rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2
  38. rom_base_bank_2
  39. rom_base_bank_3
  40. rom_base_bank_4
  41. rom_base_bank_5
  42. rw
  43. turbo_rom_adr<11>