cpldfit: version P.20131013 Xilinx Inc. Fitter Report Design Name: MegaSpeedy Date: 11- 5-2014, 10:16PM Device Used: XC95144XL-10-TQ100 Fitting Status: Successful ************************* Mapped Resource Summary ************************** Macrocells Product Terms Function Block Registers Pins Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot 117/144 ( 81%) 399 /720 ( 55%) 335/432 ( 78%) 54 /144 ( 37%) 81 /81 (100%) ** Function Block Resources ** Function Mcells FB Inps Pterms IO Block Used/Tot Used/Tot Used/Tot Used/Tot FB1 18/18* 32/54 42/90 11/11* FB2 7/18 47/54 33/90 10/10* FB3 17/18 43/54 43/90 10/10* FB4 10/18 51/54 63/90 10/10* FB5 15/18 44/54 74/90 10/10* FB6 18/18* 43/54 70/90 10/10* FB7 14/18 31/54 25/90 10/10* FB8 18/18* 44/54 49/90 10/10* ----- ----- ----- ----- 117/144 335/432 399/720 81/81 * - Resource is exhausted ** Global Control Resources ** Signal 'phi2' mapped onto global clock net GCK3. Global output enable net(s) unused. Global set/reset net(s) unused. ** Pin Resources ** Signal Type Required Mapped | Pin Type Used Total ------------------------------------|------------------------------------ Input : 28 28 | I/O : 73 73 Output : 41 41 | GCK/IO : 3 3 Bidirectional : 11 11 | GTS/IO : 4 4 GCK : 1 1 | GSR/IO : 1 1 GTS : 0 0 | GSR : 0 0 | ---- ---- Total 81 81 ** Power Data ** There are 0 macrocells in high performance mode (MCHP). There are 117 macrocells in low power mode (MCLP). End of Mapped Resource Summary ************************** Errors and Warnings *************************** WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will use the default filename of 'MegaSpeedy.ise'. INFO:Cpld - Inferring BUFG constraint for signal 'adr<11>' based upon the LOC constraint 'P22'. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored. INFO:Cpld - Inferring BUFG constraint for signal 'adr<12>' based upon the LOC constraint 'P23'. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored. WARNING:Cpld:1239 - The global clock designation (BUFG) on signal 'adr_12_IBUF' is ignored. Most likely the signal is gated and therefore cannot be used as a global control signal. WARNING:Cpld:1239 - The global clock designation (BUFG) on signal 'adr_11_IBUF' is ignored. Most likely the signal is gated and therefore cannot be used as a global control signal. ************************* Summary of Mapped Logic ************************ ** 52 Outputs ** Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init Name Pts Inps No. Type Use Mode Rate State data<2> 6 10 FB1_2 11 I/O I/O LOW SLOW data<1> 5 8 FB1_3 12 I/O I/O LOW SLOW data<0> 5 8 FB1_5 13 I/O I/O LOW SLOW ram_rom_adr<9> 1 3 FB1_14 19 I/O O LOW SLOW data<7> 12 28 FB2_5 1 GTS/I/O I/O LOW SLOW ram_rom_adr<8> 2 4 FB2_6 2 GTS/I/O O LOW SLOW turbo_speed_out 2 6 FB2_8 3 GTS/I/O O LOW SLOW data<6> 2 5 FB2_11 6 I/O I/O LOW SLOW data<5> 4 8 FB2_14 8 I/O I/O LOW SLOW data<4> 5 9 FB2_15 9 I/O I/O LOW SLOW data<3> 6 10 FB2_17 10 I/O I/O LOW SLOW ram_rom_adr<10> 3 8 FB3_5 24 I/O O LOW SLOW ram_rom_adr<11> 9 12 FB3_15 33 I/O O LOW SLOW riot_ready_inout 2 5 FB3_17 34 I/O I/O LOW SLOW track_lo<3> 7 17 FB4_2 87 I/O O LOW SLOW RESET track_lo<2> 6 17 FB4_5 89 I/O O LOW SLOW RESET track_lo<1> 7 17 FB4_6 90 I/O O LOW SLOW RESET track_lo<0> 7 17 FB4_8 91 I/O O LOW SLOW RESET ram_rom_adr<18> 5 14 FB4_9 92 I/O O LOW SLOW ram_rom_adr<17> 4 12 FB4_11 93 I/O O LOW SLOW ram_rom_adr<16> 4 12 FB4_12 94 I/O O LOW SLOW ram_rom_adr<15> 4 13 FB4_14 95 I/O O LOW SLOW ram_rom_adr<14> 10 12 FB4_15 96 I/O O LOW SLOW ram_rom_adr<13> 9 18 FB4_17 97 I/O O LOW SLOW ram_rom_adr<12> 22 17 FB5_2 35 I/O O LOW SLOW rom_ce 9 12 FB5_11 41 I/O O LOW SLOW ram_ce 14 15 FB5_12 42 I/O O LOW SLOW ram_rom_oe 1 2 FB5_17 49 I/O O LOW SLOW track_hi<5> 5 15 FB6_2 74 I/O O LOW SLOW RESET track_hi<4> 4 14 FB6_5 76 I/O O LOW SLOW RESET track_hi<3> 4 16 FB6_6 77 I/O O LOW SLOW RESET track_hi<2> 4 16 FB6_8 78 I/O O LOW SLOW RESET track_hi<1> 3 11 FB6_9 79 I/O O LOW SLOW RESET cfg_led 2 4 FB6_11 80 I/O O LOW SLOW RESET track_hi<0> 4 16 FB6_12 81 I/O O LOW SLOW RESET track_lo<6> 6 18 FB6_14 82 I/O O LOW SLOW RESET track_lo<5> 7 18 FB6_15 85 I/O O LOW SLOW RESET track_lo<4> 6 18 FB6_17 86 I/O O LOW SLOW RESET ram_rom_we 1 2 FB7_2 50 I/O O LOW SLOW centronics_data 3 5 FB7_12 58 I/O O LOW SLOW SET Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init Name Pts Inps No. Type Use Mode Rate State centronics_strobe 2 5 FB7_14 59 I/O O LOW SLOW SET centronics_clk 3 5 FB7_15 60 I/O O LOW SLOW SET i2c_data_pin 1 1 FB8_2 63 I/O I/O LOW SLOW i2c_clk_pin 1 1 FB8_5 64 I/O O LOW SLOW d7_ram_rom 2 4 FB8_6 65 I/O I/O LOW SLOW io_1050 7 10 FB8_8 66 I/O O LOW SLOW summer 2 11 FB8_9 67 I/O O LOW SLOW RESET density<2> 4 15 FB8_11 68 I/O O LOW SLOW RESET density<1> 4 15 FB8_12 70 I/O O LOW SLOW RESET density<0> 5 16 FB8_14 71 I/O O LOW SLOW RESET track_hi<6> 4 15 FB8_15 72 I/O O LOW SLOW RESET fdc_write_out 2 3 FB8_17 73 I/O O LOW SLOW ** 65 Buried Nodes ** Signal Total Total Loc Pwr Reg Init Name Pts Inps Mode State riot_ready_in_IBUF$BUF0/riot_ready_in_IBUF$BUF0_TRST 1 4 FB1_1 LOW check_1050_6810_access_cmp_eq0000/check_1050_6810_access_cmp_eq0000_D2 1 4 FB1_4 LOW $OpTx$FX_SC$508 1 3 FB1_6 LOW rom_base_bank_1 2 4 FB1_7 LOW RESET rom_base_bank_0 2 4 FB1_8 LOW RESET rom_bank_c000_enable<0> 2 4 FB1_9 LOW RESET rom_bank_c000_3 2 4 FB1_10 LOW RESET rom_bank_c000_2 2 4 FB1_11 LOW RESET rom_bank_c000_1 2 4 FB1_12 LOW RESET rom_bank_c000_0 2 4 FB1_13 LOW RESET floppy_mode<3> 2 4 FB1_15 LOW RESET floppy_mode<2> 2 4 FB1_16 LOW RESET floppy_mode<1> 2 4 FB1_17 LOW SET floppy_mode<0> 2 4 FB1_18 LOW SET turbo_rom_adr_11__or0001/turbo_rom_adr_11__or0001_D2 2 5 FB3_2 LOW rom_base_bank_5 2 4 FB3_3 LOW SET rom_base_bank_4 2 4 FB3_4 LOW SET rom_base_bank_3 2 4 FB3_6 LOW SET rom_base_bank_2 2 4 FB3_7 LOW RESET rom_bank_c000_5 2 4 FB3_8 LOW RESET rom_bank_c000_4 2 4 FB3_9 LOW RESET rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2 2 4 FB3_10 LOW ram_bank_4 2 5 FB3_11 LOW RESET ram_bank_3 2 5 FB3_12 LOW RESET ram_bank_2 2 5 FB3_13 LOW RESET ram_bank_1 2 5 FB3_14 LOW RESET ram_bank_0 2 5 FB3_16 LOW RESET i2c_data 3 6 FB3_18 LOW SET i2c_clk_and0000/i2c_clk_and0000_D2 1 14 FB5_4 LOW data_0_cmp_eq0002/data_0_cmp_eq0002_D2 1 16 FB5_5 LOW turbo_centronics_clk__or0001/turbo_centronics_clk__or0001_D2 2 4 FB5_6 LOW ram_bank_5 2 10 FB5_7 LOW RESET data_0_or0000/data_0_or0000_D2 2 20 FB5_8 LOW $OpTx$FX_DC$475 2 4 FB5_9 LOW $OpTx$FX_DC$461 2 5 FB5_10 LOW i2c_clk 3 6 FB5_14 LOW SET happy_a12 3 7 FB5_15 LOW RESET data_7_or0005/data_7_or0005_D2 5 22 FB5_16 LOW $OpTx$FX_DC$556 5 12 FB5_18 LOW $OpTx$FX_DC$515 1 7 FB6_1 LOW Signal Total Total Loc Pwr Reg Init Name Pts Inps Mode State happy_a12__or0001/happy_a12__or0001_D2 2 15 FB6_3 LOW N64/N64_D2 2 7 FB6_4 LOW $OpTx$FX_SC$520 2 11 FB6_7 LOW $OpTx$FX_DC$531 2 7 FB6_10 LOW $OpTx$FX_DC$492 3 10 FB6_13 LOW check_1050_6810_access_mux0001/check_1050_6810_access_mux0001_D2 5 8 FB6_16 LOW $OpTx$FX_DC$554 8 14 FB6_18 LOW reset_sync 1 1 FB7_6 LOW RESET reset 1 1 FB7_7 LOW RESET N104/N104_D2 1 4 FB7_8 LOW $OpTx$FX_DC$501 1 2 FB7_9 LOW turbo_rom_adr<12> 2 4 FB7_10 LOW SET turbo_rom_adr<11> 2 5 FB7_11 LOW SET rom_source_is_ram 2 4 FB7_13 LOW RESET rom_base_bank_6 2 4 FB7_16 LOW SET rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2 2 3 FB7_17 LOW $OpTx$FX_DC$517 2 4 FB7_18 LOW data_0_cmp_eq0001/data_0_cmp_eq0001_D2 1 16 FB8_1 LOW data_0_cmp_eq0000/data_0_cmp_eq0000_D2 1 16 FB8_3 LOW $OpTx$FX_DC$529 1 17 FB8_4 LOW floppy_mode_0__or0000/floppy_mode_0__or0000_D2 2 18 FB8_7 LOW N27/N27_D2 3 9 FB8_10 LOW N2/N2_D2 3 10 FB8_13 LOW N11/N11_D2 3 10 FB8_16 LOW $OpTx$FX_DC$502 3 10 FB8_18 LOW ** 29 Inputs ** Signal Loc Pin Pin Pin Name No. Type Use adr<0> FB1_6 14 I/O I adr<1> FB1_8 15 I/O I adr<2> FB1_9 16 I/O I adr<3> FB1_11 17 I/O I adr<4> FB1_12 18 I/O I adr<5> FB1_15 20 I/O I adr<11> FB1_17 22 GCK/I/O I reset_in FB2_2 99 GSR/I/O I turbo_speed_in FB2_9 4 GTS/I/O I riot_ready_in FB2_12 7 I/O I adr<12> FB3_2 23 GCK/I/O I adr<6> FB3_6 25 I/O I phi2 FB3_8 27 GCK/I/O GCK/I adr<7> FB3_9 28 I/O I adr<8> FB3_11 29 I/O I adr<9> FB3_12 30 I/O I adr<10> FB3_14 32 I/O I adr<13> FB5_5 36 I/O I adr<14> FB5_6 37 I/O I adr<15> FB5_8 39 I/O I rw FB5_9 40 I/O I archiver_a11 FB5_14 43 I/O I fdc_write_in FB5_15 46 I/O I cfg_enc_b FB7_5 52 I/O I cfg_enc_a FB7_6 53 I/O I cfg_enc_ok FB7_8 54 I/O I cfg_sw1 FB7_9 55 I/O I centronics_busy FB7_11 56 I/O I cfg_sw2 FB7_17 61 I/O I Legend: Pin No. - ~ - User Assigned ************************** Function Block Details ************************ Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X - Signal used as input to the macrocell logic. Pin No. - ~ - User Assigned *********************************** FB1 *********************************** Number of function block inputs used/remaining: 32/22 Number of signals used by logic mapping into function block: 32 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use riot_ready_in_IBUF$BUF0/riot_ready_in_IBUF$BUF0_TRST 1 0 \/1 3 FB1_1 (b) (b) data<2> 6 1<- 0 0 FB1_2 11 I/O I/O data<1> 5 0 0 0 FB1_3 12 I/O I/O check_1050_6810_access_cmp_eq0000/check_1050_6810_access_cmp_eq0000_D2 1 0 0 4 FB1_4 (b) (b) data<0> 5 0 0 0 FB1_5 13 I/O I/O $OpTx$FX_SC$508 1 0 0 4 FB1_6 14 I/O I rom_base_bank_1 2 0 0 3 FB1_7 (b) (b) rom_base_bank_0 2 0 0 3 FB1_8 15 I/O I rom_bank_c000_enable<0> 2 0 0 3 FB1_9 16 I/O I rom_bank_c000_3 2 0 0 3 FB1_10 (b) (b) rom_bank_c000_2 2 0 0 3 FB1_11 17 I/O I rom_bank_c000_1 2 0 0 3 FB1_12 18 I/O I rom_bank_c000_0 2 0 0 3 FB1_13 (b) (b) ram_rom_adr<9> 1 0 0 4 FB1_14 19 I/O O floppy_mode<3> 2 0 0 3 FB1_15 20 I/O I floppy_mode<2> 2 0 0 3 FB1_16 (b) (b) floppy_mode<1> 2 0 0 3 FB1_17 22 GCK/I/O I floppy_mode<0> 2 0 0 3 FB1_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$515 12: data_0_cmp_eq0000/data_0_cmp_eq0000_D2 23: rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2 2: N104/N104_D2 13: data_0_cmp_eq0001/data_0_cmp_eq0001_D2 24: rom_bank_c000_1 3: data<3>.PIN 14: data_0_cmp_eq0002/data_0_cmp_eq0002_D2 25: rom_bank_c000_2 4: data<2>.PIN 15: data_0_or0000/data_0_or0000_D2 26: rom_bank_c000_3 5: data<1>.PIN 16: floppy_mode<0> 27: rom_bank_c000_enable<0> 6: data<0>.PIN 17: floppy_mode<1> 28: rom_base_bank_0 7: adr<9> 18: floppy_mode<2> 29: rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2 8: cfg_enc_a 19: floppy_mode<3> 30: rom_base_bank_1 9: cfg_enc_b 20: floppy_mode_0__or0000/floppy_mode_0__or0000_D2 31: rom_base_bank_2 10: cfg_enc_ok 21: reset 32: rom_base_bank_3 11: data<7>.PIN 22: rom_bank_c000_0 Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs riot_ready_in_IBUF$BUF0/riot_ready_in_IBUF$BUF0_TRST ...............XXXX..................... 4 data<2> .........X.XXXX..X......X.X...XX........ 10 data<1> ........X..XXXX.X......X.....X.......... 8 check_1050_6810_access_cmp_eq0000/check_1050_6810_access_cmp_eq0000_D2 ...............XXXX..................... 4 data<0> .......X...XXXXX.....X.....X............ 8 $OpTx$FX_SC$508 ...........XXX.......................... 3 rom_base_bank_1 ....X...............X.......XX.......... 4 rom_base_bank_0 .....X..............X......XX........... 4 rom_bank_c000_enable<0> ..........X.........X.X...X............. 4 rom_bank_c000_3 ..X.................X.X..X.............. 4 rom_bank_c000_2 ...X................X.X.X............... 4 rom_bank_c000_1 ....X...............X.XX................ 4 rom_bank_c000_0 .....X..............XXX................. 4 ram_rom_adr<9> XX....X................................. 3 floppy_mode<3> ..X...............XXX................... 4 floppy_mode<2> ...X.............X.XX................... 4 floppy_mode<1> ....X...........X..XX................... 4 floppy_mode<0> .....X.........X...XX................... 4 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB2 *********************************** Number of function block inputs used/remaining: 47/7 Number of signals used by logic mapping into function block: 47 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB2_1 (b) (unused) 0 0 0 5 FB2_2 99 GSR/I/O I (unused) 0 0 0 5 FB2_3 (b) (unused) 0 0 \/4 1 FB2_4 (b) (b) data<7> 12 7<- 0 0 FB2_5 1 GTS/I/O I/O ram_rom_adr<8> 2 0 /\3 0 FB2_6 2 GTS/I/O O (unused) 0 0 0 5 FB2_7 (b) turbo_speed_out 2 0 0 3 FB2_8 3 GTS/I/O O (unused) 0 0 0 5 FB2_9 4 GTS/I/O I (unused) 0 0 0 5 FB2_10 (b) data<6> 2 0 0 3 FB2_11 6 I/O I/O (unused) 0 0 0 5 FB2_12 7 I/O I (unused) 0 0 0 5 FB2_13 (b) data<5> 4 0 0 1 FB2_14 8 I/O I/O data<4> 5 0 0 0 FB2_15 9 I/O I/O (unused) 0 0 \/1 4 FB2_16 (b) (b) data<3> 6 1<- 0 0 FB2_17 10 I/O I/O (unused) 0 0 0 5 FB2_18 (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$475 17: adr<4> 33: floppy_mode<1> 2: $OpTx$FX_DC$515 18: adr<5> 34: floppy_mode<2> 3: N104/N104_D2 19: adr<6> 35: floppy_mode<3> 4: i2c_data_pin.PIN 20: adr<7> 36: i2c_clk_and0000/i2c_clk_and0000_D2 5: riot_ready_inout.PIN 21: adr<8> 37: rom_bank_c000_3 6: d7_ram_rom.PIN 22: adr<9> 38: rom_bank_c000_4 7: adr<0> 23: centronics_busy 39: rom_bank_c000_5 8: adr<10> 24: cfg_sw1 40: rom_bank_c000_enable<0> 9: adr<11> 25: cfg_sw2 41: rom_base_bank_3 10: adr<12> 26: check_1050_6810_access_cmp_eq0000/check_1050_6810_access_cmp_eq0000_D2 42: rom_base_bank_4 11: adr<13> 27: data_0_cmp_eq0000/data_0_cmp_eq0000_D2 43: rom_base_bank_5 12: adr<14> 28: data_0_cmp_eq0001/data_0_cmp_eq0001_D2 44: rom_base_bank_6 13: adr<15> 29: data_0_cmp_eq0002/data_0_cmp_eq0002_D2 45: rom_source_is_ram 14: adr<1> 30: data_0_or0000/data_0_or0000_D2 46: rw 15: adr<2> 31: data_7_or0005/data_7_or0005_D2 47: turbo_speed_in 16: adr<3> 32: floppy_mode<0> Signal 1 2 3 4 5 FB Name 0----+----0----+----0----+----0----+----0----+----0 Inputs data<7> X..X.XXXXXXXXXXXXXXXXXX..X.XX.X....X...X....XX.... 28 ram_rom_adr<8> .XX.................XX............................ 4 turbo_speed_out ....X..........................XXXX...........X... 6 data<6> ..........................XXXX.............X...... 5 data<5> ..........................XXXX........XX..XX...... 8 data<4> ........................X.XXXX.......X.X.XX....... 9 data<3> .......................X..XXXX....X.X..XXX........ 10 0----+----1----+----2----+----3----+----4----+----5 0 0 0 0 0 *********************************** FB3 *********************************** Number of function block inputs used/remaining: 43/11 Number of signals used by logic mapping into function block: 43 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB3_1 (b) turbo_rom_adr_11__or0001/turbo_rom_adr_11__or0001_D2 2 0 0 3 FB3_2 23 GCK/I/O I rom_base_bank_5 2 0 0 3 FB3_3 (b) (b) rom_base_bank_4 2 0 0 3 FB3_4 (b) (b) ram_rom_adr<10> 3 0 0 2 FB3_5 24 I/O O rom_base_bank_3 2 0 0 3 FB3_6 25 I/O I rom_base_bank_2 2 0 0 3 FB3_7 (b) (b) rom_bank_c000_5 2 0 0 3 FB3_8 27 GCK/I/O GCK/I rom_bank_c000_4 2 0 0 3 FB3_9 28 I/O I rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2 2 0 0 3 FB3_10 (b) (b) ram_bank_4 2 0 0 3 FB3_11 29 I/O I ram_bank_3 2 0 0 3 FB3_12 30 I/O I ram_bank_2 2 0 0 3 FB3_13 (b) (b) ram_bank_1 2 0 \/2 1 FB3_14 32 I/O I ram_rom_adr<11> 9 4<- 0 0 FB3_15 33 I/O O ram_bank_0 2 0 /\2 1 FB3_16 (b) (b) riot_ready_inout 2 0 0 3 FB3_17 34 I/O I/O i2c_data 3 0 0 2 FB3_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$475 16: adr<1> 30: ram_bank_3 2: $OpTx$FX_DC$515 17: adr<7> 31: ram_bank_4 3: $OpTx$FX_SC$520 18: archiver_a11 32: reset 4: N104/N104_D2 19: check_1050_6810_access_cmp_eq0000/check_1050_6810_access_cmp_eq0000_D2 33: riot_ready_in 5: d7_ram_rom.PIN 20: data_0_cmp_eq0001/data_0_cmp_eq0001_D2 34: rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2 6: data<5>.PIN 21: floppy_mode<0> 35: rom_bank_c000_4 7: data<4>.PIN 22: floppy_mode<1> 36: rom_bank_c000_5 8: data<3>.PIN 23: floppy_mode<2> 37: rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2 9: data<2>.PIN 24: floppy_mode<3> 38: rom_base_bank_2 10: data<1>.PIN 25: i2c_clk_and0000/i2c_clk_and0000_D2 39: rom_base_bank_3 11: data<0>.PIN 26: i2c_data 40: rom_base_bank_4 12: N27/N27_D2 27: ram_bank_0 41: rom_base_bank_5 13: adr<10> 28: ram_bank_1 42: rw 14: adr<11> 29: ram_bank_2 43: turbo_rom_adr<11> 15: adr<12> Signal 1 2 3 4 5 FB Name 0----+----0----+----0----+----0----+----0----+----0 Inputs turbo_rom_adr_11__or0001/turbo_rom_adr_11__or0001_D2 ....X........XX...X............X.................. 5 rom_base_bank_5 .....X.........................X....X...X......... 4 rom_base_bank_4 ......X........................X....X..X.......... 4 ram_rom_adr<10> ...X........X.X.X...XXXX.......................... 8 rom_base_bank_3 .......X.......................X....X.X........... 4 rom_base_bank_2 ........X......................X....XX............ 4 rom_bank_c000_5 .....X.........................X.X.X.............. 4 rom_bank_c000_4 ......X........................X.XX............... 4 rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2 X..................X...........X.........X........ 4 ram_bank_4 ..X...X....X..................XX.................. 5 ram_bank_3 ..X....X...X.................X.X.................. 5 ram_bank_2 ..X.....X..X................X..X.................. 5 ram_bank_1 ..X......X.X...............X...X.................. 5 ram_rom_adr<11> .X.X........XXX..X..XXXX.................XX....... 12 ram_bank_0 ..X.......XX..............X....X.................. 5 riot_ready_inout ....................XXXX........X................. 5 i2c_data X..............X........XX.....X.........X........ 6 0----+----1----+----2----+----3----+----4----+----5 0 0 0 0 0 *********************************** FB4 *********************************** Number of function block inputs used/remaining: 51/3 Number of signals used by logic mapping into function block: 51 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 \/1 4 FB4_1 (b) (b) track_lo<3> 7 2<- 0 0 FB4_2 87 I/O O (unused) 0 0 /\1 4 FB4_3 (b) (b) (unused) 0 0 \/1 4 FB4_4 (b) (b) track_lo<2> 6 1<- 0 0 FB4_5 89 I/O O track_lo<1> 7 2<- 0 0 FB4_6 90 I/O O (unused) 0 0 /\2 3 FB4_7 (b) (b) track_lo<0> 7 2<- 0 0 FB4_8 91 I/O O ram_rom_adr<18> 5 2<- /\2 0 FB4_9 92 I/O O (unused) 0 0 /\2 3 FB4_10 (b) (b) ram_rom_adr<17> 4 0 0 1 FB4_11 93 I/O O ram_rom_adr<16> 4 0 0 1 FB4_12 94 I/O O (unused) 0 0 0 5 FB4_13 (b) ram_rom_adr<15> 4 0 \/1 0 FB4_14 95 I/O O ram_rom_adr<14> 10 5<- 0 0 FB4_15 96 I/O O (unused) 0 0 /\4 1 FB4_16 (b) (b) ram_rom_adr<13> 9 4<- 0 0 FB4_17 97 I/O O (unused) 0 0 /\4 1 FB4_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$461 18: adr<13> 35: rom_bank_c000_2 2: $OpTx$FX_DC$475 19: adr<14> 36: rom_bank_c000_3 3: $OpTx$FX_DC$502 20: adr<15> 37: rom_bank_c000_4 4: $OpTx$FX_DC$517 21: adr<1> 38: rom_bank_c000_5 5: $OpTx$FX_DC$531 22: floppy_mode<0> 39: rom_bank_c000_enable<0> 6: $OpTx$FX_DC$554 23: floppy_mode<1> 40: rom_base_bank_1 7: $OpTx$FX_DC$556 24: floppy_mode<2> 41: rom_base_bank_2 8: N104/N104_D2 25: floppy_mode<3> 42: rom_base_bank_3 9: N11/N11_D2 26: ram_bank_0 43: rom_base_bank_4 10: data<3>.PIN 27: ram_bank_1 44: rom_base_bank_5 11: data<2>.PIN 28: ram_bank_2 45: rom_base_bank_6 12: data<1>.PIN 29: ram_bank_3 46: rom_source_is_ram 13: data<0>.PIN 30: ram_bank_4 47: rw 14: N64/N64_D2 31: ram_bank_5 48: track_lo<0> 15: adr<0> 32: reset 49: track_lo<1> 16: adr<11> 33: rom_bank_c000_0 50: track_lo<2> 17: adr<12> 34: rom_bank_c000_1 51: track_lo<3> Signal 1 2 3 4 5 6 FB Name 0----+----0----+----0----+----0----+----0----+----0----+----0 Inputs track_lo<3> X.......XXXXX.X...XXXXXXX......X..............X...X......... 17 track_lo<2> X.......XXXXX.X...XXXXXXX......X..............X..X.......... 17 track_lo<1> X.......XXXXX.X...XXXXXXX......X..............X.X........... 17 track_lo<0> X.......XXXXX.X...XXXXXXX......X..............XX............ 17 ram_rom_adr<18> .X.X.........X...XXX.XXXX.....X......XX.....X............... 14 ram_rom_adr<17> .X.X.........X...XXX...XX....X......X.X....X................ 12 ram_rom_adr<16> .X.X.........X...XXX...XX...X......X..X...X................. 12 ram_rom_adr<15> .X...X.X.........XXX...XX..X......X...X..X...X.............. 13 ram_rom_adr<14> .XX...X..........XXX...XX.X......X......X....X.............. 12 ram_rom_adr<13> .XX.X..X.......XXXXX.XXXXX......X......X.....XX............. 18 0----+----1----+----2----+----3----+----4----+----5----+----6 0 0 0 0 0 0 *********************************** FB5 *********************************** Number of function block inputs used/remaining: 44/10 Number of signals used by logic mapping into function block: 44 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 \/5 0 FB5_1 (b) (b) ram_rom_adr<12> 22 17<- 0 0 FB5_2 35 I/O O (unused) 0 0 /\5 0 FB5_3 (b) (b) i2c_clk_and0000/i2c_clk_and0000_D2 1 1<- /\5 0 FB5_4 (b) (b) data_0_cmp_eq0002/data_0_cmp_eq0002_D2 1 0 /\1 3 FB5_5 36 I/O I turbo_centronics_clk__or0001/turbo_centronics_clk__or0001_D2 2 0 0 3 FB5_6 37 I/O I ram_bank_5 2 0 0 3 FB5_7 (b) (b) data_0_or0000/data_0_or0000_D2 2 0 0 3 FB5_8 39 I/O I $OpTx$FX_DC$475 2 0 \/1 2 FB5_9 40 I/O I $OpTx$FX_DC$461 2 1<- \/4 0 FB5_10 (b) (b) rom_ce 9 4<- 0 0 FB5_11 41 I/O O ram_ce 14 9<- 0 0 FB5_12 42 I/O O (unused) 0 0 /\5 0 FB5_13 (b) (b) i2c_clk 3 2<- /\4 0 FB5_14 43 I/O I happy_a12 3 0 /\2 0 FB5_15 46 I/O I data_7_or0005/data_7_or0005_D2 5 0 0 0 FB5_16 (b) (b) ram_rom_oe 1 0 \/2 2 FB5_17 49 I/O O $OpTx$FX_DC$556 5 2<- \/2 0 FB5_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$475 16: adr<15> 31: happy_a12 2: $OpTx$FX_DC$501 17: adr<1> 32: happy_a12__or0001/happy_a12__or0001_D2 3: $OpTx$FX_DC$502 18: adr<2> 33: i2c_clk 4: $OpTx$FX_DC$515 19: adr<3> 34: i2c_clk_and0000/i2c_clk_and0000_D2 5: $OpTx$FX_DC$556 20: adr<4> 35: phi2 6: $OpTx$FX_SC$508 21: adr<5> 36: ram_bank_3 7: N104/N104_D2 22: adr<6> 37: ram_bank_4 8: data<5>.PIN 23: adr<7> 38: ram_bank_5 9: N27/N27_D2 24: adr<8> 39: reset 10: adr<0> 25: adr<9> 40: rom_bank_c000_enable<0> 11: adr<10> 26: check_1050_6810_access_cmp_eq0000/check_1050_6810_access_cmp_eq0000_D2 41: rom_base_bank_0 12: adr<11> 27: floppy_mode<0> 42: rom_source_is_ram 13: adr<12> 28: floppy_mode<1> 43: rw 14: adr<13> 29: floppy_mode<2> 44: turbo_rom_adr<12> 15: adr<14> 30: floppy_mode<3> Signal 1 2 3 4 5 FB Name 0----+----0----+----0----+----0----+----0----+----0 Inputs ram_rom_adr<12> ...X..X...XXXXXX..........XXXXX.........XXXX...... 17 i2c_clk_and0000/i2c_clk_and0000_D2 ..........XXXXXX.XXXXXXXX......................... 14 data_0_cmp_eq0002/data_0_cmp_eq0002_D2 .........XXXXXXXXXXXXXXXX......................... 16 turbo_centronics_clk__or0001/turbo_centronics_clk__or0001_D2 ...........XX............X............X........... 4 ram_bank_5 X......XX...XXXX.....................XX...X....... 10 data_0_or0000/data_0_or0000_D2 X....X...XXXXXXXXXXXXXXXX.........X.......X....... 20 $OpTx$FX_DC$475 ..........................XXXX.................... 4 $OpTx$FX_DC$461 .............X............XXXX.................... 5 rom_ce ...........XXXXX..........XXXX.........X.XX....... 12 ram_ce ..X.X.......XXXX..........XXXX.....XX..X.XX....... 15 i2c_clk X........X......................XX....X...X....... 6 happy_a12 .........X......XXX...........XX......X........... 7 data_7_or0005/data_7_or0005_D2 XX...X...XXXXXXXXXXXXXXXXX........X.......X....... 22 ram_rom_oe ..................................X.......X....... 2 $OpTx$FX_DC$556 ...X..X....XXXXX..........XXXX............X....... 12 0----+----1----+----2----+----3----+----4----+----5 0 0 0 0 0 *********************************** FB6 *********************************** Number of function block inputs used/remaining: 43/11 Number of signals used by logic mapping into function block: 43 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use $OpTx$FX_DC$515 1 0 /\4 0 FB6_1 (b) (b) track_hi<5> 5 0 0 0 FB6_2 74 I/O O happy_a12__or0001/happy_a12__or0001_D2 2 0 0 3 FB6_3 (b) (b) N64/N64_D2 2 0 0 3 FB6_4 (b) (b) track_hi<4> 4 0 0 1 FB6_5 76 I/O O track_hi<3> 4 0 0 1 FB6_6 77 I/O O $OpTx$FX_SC$520 2 0 0 3 FB6_7 (b) (b) track_hi<2> 4 0 0 1 FB6_8 78 I/O O track_hi<1> 3 0 0 2 FB6_9 79 I/O O $OpTx$FX_DC$531 2 0 0 3 FB6_10 (b) (b) cfg_led 2 0 0 3 FB6_11 80 I/O O track_hi<0> 4 0 \/1 0 FB6_12 81 I/O O $OpTx$FX_DC$492 3 1<- \/3 0 FB6_13 (b) (b) track_lo<6> 6 3<- \/2 0 FB6_14 82 I/O O track_lo<5> 7 2<- 0 0 FB6_15 85 I/O O check_1050_6810_access_mux0001/check_1050_6810_access_mux0001_D2 5 0 0 0 FB6_16 (b) (b) track_lo<4> 6 1<- 0 0 FB6_17 86 I/O O $OpTx$FX_DC$554 8 4<- /\1 0 FB6_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$461 16: adr<12> 30: floppy_mode<2> 2: $OpTx$FX_DC$475 17: adr<13> 31: floppy_mode<3> 3: $OpTx$FX_DC$529 18: adr<14> 32: reset 4: N11/N11_D2 19: adr<15> 33: rom_bank_c000_enable<0> 5: data<6>.PIN 20: adr<1> 34: rw 6: data<5>.PIN 21: adr<4> 35: track_hi<0> 7: data<4>.PIN 22: adr<5> 36: track_hi<1> 8: data<3>.PIN 23: adr<6> 37: track_hi<2> 9: data<2>.PIN 24: adr<7> 38: track_hi<3> 10: data<1>.PIN 25: adr<8> 39: track_hi<4> 11: data<0>.PIN 26: adr<9> 40: track_hi<5> 12: N2/N2_D2 27: cfg_led 41: track_lo<4> 13: adr<0> 28: floppy_mode<0> 42: track_lo<5> 14: adr<10> 29: floppy_mode<1> 43: track_lo<6> 15: adr<11> Signal 1 2 3 4 5 FB Name 0----+----0----+----0----+----0----+----0----+----0 Inputs $OpTx$FX_DC$515 .............X.X.......X...XXXX................... 7 track_hi<5> X....XX....XX....XXX.......XXXXX.X.....X.......... 15 happy_a12__or0001/happy_a12__or0001_D2 .............XX..XX.XXXXXX.XXXXX.................. 15 N64/N64_D2 .X..............XXX..........XX.X................. 7 track_hi<4> X.....X....XX....XXX.......XXXXX.X....X........... 14 track_hi<3> X....XXX...XX....XXX.......XXXXX.X...X............ 16 $OpTx$FX_SC$520 .X.............XXXX........XXXXX.X................ 11 track_hi<2> X....XX.X..XX....XXX.......XXXXX.X..X............. 16 track_hi<1> X........X.XX....XXX..........XX.X.X.............. 11 $OpTx$FX_DC$531 .............X.X.......X...XXXX................... 7 cfg_led ..X.......X...............X....X.................. 4 track_hi<0> X....XX...XXX....XXX.......XXXXX.XX............... 16 $OpTx$FX_DC$492 ............X...XXXX.......XXXX..X................ 10 track_lo<6> X..XX..XXXX.X....XXX.......XXXXX.X........X....... 18 track_lo<5> X..X.X.XXXX.X....XXX.......XXXXX.X.......X........ 18 check_1050_6810_access_mux0001/check_1050_6810_access_mux0001_D2 ...............XXXX........XXXX................... 8 track_lo<4> X..X..XXXXX.X....XXX.......XXXXX.X......X......... 18 $OpTx$FX_DC$554 .X...........XXXXXX....X...XXXX.XX................ 14 0----+----1----+----2----+----3----+----4----+----5 0 0 0 0 0 *********************************** FB7 *********************************** Number of function block inputs used/remaining: 31/23 Number of signals used by logic mapping into function block: 31 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB7_1 (b) ram_rom_we 1 0 0 4 FB7_2 50 I/O O (unused) 0 0 0 5 FB7_3 (b) (unused) 0 0 0 5 FB7_4 (b) (unused) 0 0 0 5 FB7_5 52 I/O I reset_sync 1 0 0 4 FB7_6 53 I/O I reset 1 0 0 4 FB7_7 (b) (b) N104/N104_D2 1 0 0 4 FB7_8 54 I/O I $OpTx$FX_DC$501 1 0 0 4 FB7_9 55 I/O I turbo_rom_adr<12> 2 0 0 3 FB7_10 (b) (b) turbo_rom_adr<11> 2 0 0 3 FB7_11 56 I/O I centronics_data 3 0 0 2 FB7_12 58 I/O O rom_source_is_ram 2 0 0 3 FB7_13 (b) (b) centronics_strobe 2 0 0 3 FB7_14 59 I/O O centronics_clk 3 0 0 2 FB7_15 60 I/O O rom_base_bank_6 2 0 0 3 FB7_16 (b) (b) rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2 2 0 0 3 FB7_17 61 I/O I $OpTx$FX_DC$517 2 0 0 3 FB7_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$475 12: centronics_clk 22: reset_sync 2: $OpTx$FX_DC$502 13: centronics_data 23: rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2 3: $OpTx$FX_DC$556 14: centronics_strobe 24: rom_base_bank_6 4: d7_ram_rom.PIN 15: check_1050_6810_access_mux0001/check_1050_6810_access_mux0001_D2 25: rom_ce 5: data<6>.PIN 16: data<7>.PIN 26: rom_source_is_ram 6: data<5>.PIN 17: data_0_cmp_eq0002/data_0_cmp_eq0002_D2 27: rw 7: data<4>.PIN 18: phi2 28: turbo_centronics_clk__or0001/turbo_centronics_clk__or0001_D2 8: N64/N64_D2 19: ram_ce 29: turbo_rom_adr<11> 9: adr<10> 20: reset 30: turbo_rom_adr<12> 10: adr<7> 21: reset_in 31: turbo_rom_adr_11__or0001/turbo_rom_adr_11__or0001_D2 11: adr<9> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs ram_rom_we .................X........X............. 2 reset_sync ....................X................... 1 reset .....................X.................. 1 N104/N104_D2 ........XXX...X......................... 4 $OpTx$FX_DC$501 ..................X.....X............... 2 turbo_rom_adr<12> .....X.............X.........XX......... 4 turbo_rom_adr<11> ....X.X............X........X.X......... 5 centronics_data ...X.X......X......X.......X............ 5 rom_source_is_ram ...............X...X..X..X.............. 4 centronics_strobe ...XX........X.....X.......X............ 5 centronics_clk ...X..X....X.......X.......X............ 5 rom_base_bank_6 ....X..............X..XX................ 4 rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2 X...............X..X.................... 3 $OpTx$FX_DC$517 .XX....X.................X.............. 4 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB8 *********************************** Number of function block inputs used/remaining: 44/10 Number of signals used by logic mapping into function block: 44 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use data_0_cmp_eq0001/data_0_cmp_eq0001_D2 1 0 0 4 FB8_1 (b) (b) i2c_data_pin 1 0 0 4 FB8_2 63 I/O I/O data_0_cmp_eq0000/data_0_cmp_eq0000_D2 1 0 0 4 FB8_3 (b) (b) $OpTx$FX_DC$529 1 0 0 4 FB8_4 (b) (b) i2c_clk_pin 1 0 0 4 FB8_5 64 I/O O d7_ram_rom 2 0 0 3 FB8_6 65 I/O I/O floppy_mode_0__or0000/floppy_mode_0__or0000_D2 2 0 \/1 2 FB8_7 (b) (b) io_1050 7 2<- 0 0 FB8_8 66 I/O O summer 2 0 /\1 2 FB8_9 67 I/O O N27/N27_D2 3 0 0 2 FB8_10 (b) (b) density<2> 4 0 0 1 FB8_11 68 I/O O density<1> 4 0 0 1 FB8_12 70 I/O O N2/N2_D2 3 0 0 2 FB8_13 (b) (b) density<0> 5 0 0 0 FB8_14 71 I/O O track_hi<6> 4 0 0 1 FB8_15 72 I/O O N11/N11_D2 3 0 0 2 FB8_16 (b) (b) fdc_write_out 2 0 0 3 FB8_17 73 I/O O $OpTx$FX_DC$502 3 0 0 2 FB8_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$461 16: adr<14> 31: density<1> 2: $OpTx$FX_DC$475 17: adr<15> 32: density<2> 3: $OpTx$FX_DC$492 18: adr<1> 33: fdc_write_in 4: $OpTx$FX_DC$501 19: adr<2> 34: floppy_mode<0> 5: data<6>.PIN 20: adr<3> 35: floppy_mode<1> 6: data<5>.PIN 21: adr<4> 36: floppy_mode<2> 7: data<2>.PIN 22: adr<5> 37: floppy_mode<3> 8: data<1>.PIN 23: adr<6> 38: i2c_clk 9: data<0>.PIN 24: adr<7> 39: i2c_data 10: N2/N2_D2 25: adr<8> 40: phi2 11: adr<0> 26: adr<9> 41: reset 12: adr<10> 27: archiver_a11 42: riot_ready_in_IBUF$BUF0/riot_ready_in_IBUF$BUF0_TRST 13: adr<11> 28: check_1050_6810_access_mux0001/check_1050_6810_access_mux0001_D2 43: rw 14: adr<12> 29: data<7>.PIN 44: track_hi<6> 15: adr<13> 30: density<0> Signal 1 2 3 4 5 FB Name 0----+----0----+----0----+----0----+----0----+----0 Inputs data_0_cmp_eq0001/data_0_cmp_eq0001_D2 ..........XXXXXXXXXXXXXXXX........................ 16 i2c_data_pin ......................................X........... 1 data_0_cmp_eq0000/data_0_cmp_eq0000_D2 ..........XXXXXXXXXXXXXXXX........................ 16 $OpTx$FX_DC$529 .X........XXXXXXXXXXXXXXXX........................ 17 i2c_clk_pin .....................................X............ 1 d7_ram_rom ...X........................X..........X..X....... 4 floppy_mode_0__or0000/floppy_mode_0__or0000_D2 .X........XXXXXXXXXXXXXXXX..............X......... 18 io_1050 ...........XXX.........X.X.X.....XXXX............. 10 summer ..........X...XXXX...............XXXX...X.X....... 11 N27/N27_D2 .............XXXX................XXXX.....X....... 9 density<2> X.X.X.X...X....XXX.............X.XXXX...X.X....... 15 density<1> X.X....X..X....XXX..........X.X..XXXX...X.X....... 15 N2/N2_D2 ..........X...XXXX...............XXXX.....X....... 10 density<0> X.X.X...X.X....XXX..........XX...XXXX...X.X....... 16 track_hi<6> X...XX...XX....XXX...............XXXX...X.XX...... 15 N11/N11_D2 ..........X...XXXX...............XXXX.....X....... 10 fdc_write_out ..........................X.....X........X........ 3 $OpTx$FX_DC$502 ...........XXXXXX................XXXX............. 10 0----+----1----+----2----+----3----+----4----+----5 0 0 0 0 0 ******************************* Equations ******************************** ********** Mapped Logic ********** $OpTx$FX_DC$461 <= ((NOT floppy_mode(3) AND floppy_mode(0) AND NOT floppy_mode(2) AND NOT floppy_mode(1)) OR (NOT floppy_mode(2) AND NOT adr(13))); $OpTx$FX_DC$475 <= ((NOT floppy_mode(3) AND floppy_mode(0) AND NOT floppy_mode(2) AND floppy_mode(1)) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND NOT floppy_mode(2) AND NOT floppy_mode(1))); $OpTx$FX_DC$492 <= ((NOT adr(0) AND NOT floppy_mode(3) AND floppy_mode(0) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND adr(1)) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15)) OR (NOT adr(0) AND NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT adr(13) AND adr(14) AND NOT rw AND NOT adr(15) AND adr(1))); $OpTx$FX_DC$501 <= (ram_ce AND rom_ce); $OpTx$FX_DC$502 <= ((NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT adr(13) AND NOT adr(14) AND adr(15)) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND NOT adr(14) AND adr(15)) OR (NOT adr(12) AND floppy_mode(3) AND floppy_mode(0) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND NOT adr(10) AND adr(11))); $OpTx$FX_DC$515 <= (NOT adr(12) AND NOT floppy_mode(3) AND floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND NOT adr(7) AND NOT adr(10)); $OpTx$FX_DC$517 <= ((NOT rom_source_is_ram AND NOT $OpTx$FX_DC$556 AND NOT $OpTx$FX_DC$502) OR (NOT $OpTx$FX_DC$556 AND NOT $OpTx$FX_DC$502 AND N64/N64_D2)); $OpTx$FX_DC$529 <= (adr(4) AND adr(3) AND adr(0) AND adr(12) AND adr(13) AND adr(14) AND NOT adr(15) AND NOT adr(9) AND NOT adr(7) AND NOT adr(10) AND NOT adr(5) AND NOT adr(1) AND NOT adr(2) AND NOT adr(11) AND NOT adr(6) AND NOT adr(8) AND $OpTx$FX_DC$475); $OpTx$FX_DC$531 <= ((NOT floppy_mode(3) AND NOT floppy_mode(2)) OR (NOT adr(12) AND NOT floppy_mode(3) AND floppy_mode(0) AND floppy_mode(1) AND NOT adr(7) AND NOT adr(10))); $OpTx$FX_DC$554 <= ((adr(12) AND floppy_mode(3) AND NOT floppy_mode(0) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND NOT rw) OR (NOT adr(12) AND floppy_mode(3) AND floppy_mode(0) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND NOT adr(10) AND adr(11)) OR (NOT adr(12) AND NOT floppy_mode(3) AND floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND NOT adr(7) AND NOT adr(10)) OR (floppy_mode(3) AND NOT floppy_mode(0) AND NOT floppy_mode(2) AND floppy_mode(1) AND adr(13) AND NOT adr(14) AND NOT adr(15)) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT adr(14) AND adr(15)) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(1) AND NOT adr(14) AND adr(15)) OR (adr(12) AND floppy_mode(3) AND NOT floppy_mode(0) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND NOT adr(11)) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND rom_bank_c000_enable(0) AND NOT adr(13) AND adr(15) AND $OpTx$FX_DC$475)); $OpTx$FX_DC$556 <= ((N104/N104_D2) OR ($OpTx$FX_DC$515) OR (adr(12) AND floppy_mode(3) AND NOT floppy_mode(0) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND NOT adr(11)) OR (floppy_mode(3) AND NOT floppy_mode(0) AND NOT floppy_mode(2) AND floppy_mode(1) AND adr(13) AND NOT adr(14) AND NOT adr(15)) OR (adr(12) AND floppy_mode(3) AND NOT floppy_mode(0) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND NOT rw)); $OpTx$FX_SC$508 <= (NOT data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2 AND NOT data_0_cmp_eq0002/data_0_cmp_eq0002_D2); $OpTx$FX_SC$520 <= ((NOT adr(12) AND adr(13) AND adr(14) AND NOT rw AND NOT adr(15) AND reset AND $OpTx$FX_DC$475) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND NOT floppy_mode(2) AND floppy_mode(1) AND adr(13) AND adr(14) AND NOT rw AND NOT adr(15) AND reset)); N104/N104_D2 <= (NOT adr(9) AND NOT adr(7) AND NOT adr(10) AND check_1050_6810_access_mux0001/check_1050_6810_access_mux0001_D2); N11/N11_D2 <= ((NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15)) OR (NOT adr(0) AND NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT adr(13) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT adr(1)) OR (NOT adr(0) AND NOT floppy_mode(3) AND floppy_mode(0) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT adr(1))); N2/N2_D2 <= ((NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15)) OR (adr(0) AND NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT adr(13) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT adr(1)) OR (adr(0) AND NOT floppy_mode(3) AND floppy_mode(0) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT adr(1))); N27/N27_D2 <= ((NOT adr(12) AND NOT floppy_mode(3) AND NOT floppy_mode(0) AND NOT floppy_mode(2) AND adr(13) AND adr(14) AND NOT rw AND NOT adr(15)) OR (NOT adr(12) AND NOT floppy_mode(3) AND NOT floppy_mode(2) AND floppy_mode(1) AND adr(13) AND adr(14) AND NOT rw AND NOT adr(15)) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND NOT floppy_mode(2) AND floppy_mode(1) AND adr(13) AND adr(14) AND NOT rw AND NOT adr(15))); N64/N64_D2 <= ((NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT adr(14) AND adr(15)) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND rom_bank_c000_enable(0) AND NOT adr(13) AND adr(15) AND $OpTx$FX_DC$475)); FDCPE_centronics_clk: FDCPE port map (centronics_clk,centronics_clk_D,NOT phi2,'0','0'); centronics_clk_D <= ((centronics_clk AND NOT turbo_centronics_clk__or0001/turbo_centronics_clk__or0001_D2) OR (NOT reset AND turbo_centronics_clk__or0001/turbo_centronics_clk__or0001_D2) OR (d7_ram_rom.PIN AND data(4).PIN AND turbo_centronics_clk__or0001/turbo_centronics_clk__or0001_D2)); FDCPE_centronics_data: FDCPE port map (centronics_data,centronics_data_D,NOT phi2,'0','0'); centronics_data_D <= ((centronics_data AND NOT turbo_centronics_clk__or0001/turbo_centronics_clk__or0001_D2) OR (NOT reset AND turbo_centronics_clk__or0001/turbo_centronics_clk__or0001_D2) OR (d7_ram_rom.PIN AND data(5).PIN AND turbo_centronics_clk__or0001/turbo_centronics_clk__or0001_D2)); FDCPE_centronics_strobe: FDCPE port map (centronics_strobe,centronics_strobe_D,NOT phi2,'0','0'); centronics_strobe_D <= ((NOT centronics_strobe AND NOT turbo_centronics_clk__or0001/turbo_centronics_clk__or0001_D2) OR (NOT data(6).PIN AND d7_ram_rom.PIN AND reset AND turbo_centronics_clk__or0001/turbo_centronics_clk__or0001_D2)); FDCPE_cfg_led: FDCPE port map (cfg_led,cfg_led_D,NOT phi2,'0','0'); cfg_led_D <= ((data(0).PIN AND reset AND $OpTx$FX_DC$529) OR (cfg_led AND reset AND NOT $OpTx$FX_DC$529)); check_1050_6810_access_cmp_eq0000/check_1050_6810_access_cmp_eq0000_D2 <= (NOT floppy_mode(3) AND floppy_mode(0) AND floppy_mode(2) AND NOT floppy_mode(1)); check_1050_6810_access_mux0001/check_1050_6810_access_mux0001_D2 <= ((NOT adr(12) AND NOT floppy_mode(3) AND floppy_mode(2) AND NOT floppy_mode(1)) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT adr(14) AND NOT adr(15)) OR (NOT adr(12) AND floppy_mode(3) AND NOT floppy_mode(0) AND NOT floppy_mode(2) AND NOT floppy_mode(1)) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(1) AND NOT adr(14) AND NOT adr(15)) OR (NOT floppy_mode(0) AND NOT floppy_mode(2) AND floppy_mode(1) AND NOT adr(13) AND NOT adr(14) AND NOT adr(15))); d7_ram_rom_I <= data(7).PIN; d7_ram_rom <= d7_ram_rom_I when d7_ram_rom_OE = '1' else 'Z'; d7_ram_rom_OE <= (phi2 AND NOT rw AND NOT $OpTx$FX_DC$501); data_I(0) <= ((cfg_enc_a AND data_0_cmp_eq0000/data_0_cmp_eq0000_D2) OR (rom_bank_c000_0 AND data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2) OR (floppy_mode(0) AND NOT data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2 AND NOT data_0_cmp_eq0002/data_0_cmp_eq0002_D2) OR (rom_base_bank_0 AND NOT data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2 AND data_0_cmp_eq0002/data_0_cmp_eq0002_D2)); data(0) <= data_I(0) when data_OE(0) = '1' else 'Z'; data_OE(0) <= data_0_or0000/data_0_or0000_D2; data_I(1) <= ((cfg_enc_b AND data_0_cmp_eq0000/data_0_cmp_eq0000_D2) OR (rom_bank_c000_1 AND data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2) OR (floppy_mode(1) AND NOT data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2 AND NOT data_0_cmp_eq0002/data_0_cmp_eq0002_D2) OR (rom_base_bank_1 AND NOT data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2 AND data_0_cmp_eq0002/data_0_cmp_eq0002_D2)); data(1) <= data_I(1) when data_OE(1) = '1' else 'Z'; data_OE(1) <= data_0_or0000/data_0_or0000_D2; data_I(2) <= ((floppy_mode(2) AND NOT data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2 AND NOT data_0_cmp_eq0002/data_0_cmp_eq0002_D2) OR (cfg_enc_ok AND data_0_cmp_eq0000/data_0_cmp_eq0000_D2) OR (rom_bank_c000_enable(0) AND rom_bank_c000_2 AND data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2) OR (NOT rom_bank_c000_enable(0) AND rom_base_bank_3 AND data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2) OR (rom_base_bank_2 AND NOT data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2 AND data_0_cmp_eq0002/data_0_cmp_eq0002_D2)); data(2) <= data_I(2) when data_OE(2) = '1' else 'Z'; data_OE(2) <= data_0_or0000/data_0_or0000_D2; data_I(3) <= ((floppy_mode(3) AND NOT data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2 AND NOT data_0_cmp_eq0002/data_0_cmp_eq0002_D2) OR (cfg_sw1 AND data_0_cmp_eq0000/data_0_cmp_eq0000_D2) OR (rom_bank_c000_enable(0) AND rom_bank_c000_3 AND data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2) OR (NOT rom_bank_c000_enable(0) AND rom_base_bank_4 AND data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2) OR (rom_base_bank_3 AND NOT data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2 AND data_0_cmp_eq0002/data_0_cmp_eq0002_D2)); data(3) <= data_I(3) when data_OE(3) = '1' else 'Z'; data_OE(3) <= data_0_or0000/data_0_or0000_D2; data_I(4) <= ((cfg_sw2 AND data_0_cmp_eq0000/data_0_cmp_eq0000_D2) OR (rom_bank_c000_enable(0) AND rom_bank_c000_4 AND data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2) OR (NOT rom_bank_c000_enable(0) AND rom_base_bank_5 AND data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2) OR (rom_base_bank_4 AND NOT data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2 AND data_0_cmp_eq0002/data_0_cmp_eq0002_D2)); data(4) <= data_I(4) when data_OE(4) = '1' else 'Z'; data_OE(4) <= data_0_or0000/data_0_or0000_D2; data_I(5) <= ((rom_bank_c000_enable(0) AND rom_bank_c000_5 AND data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2) OR (NOT rom_bank_c000_enable(0) AND rom_base_bank_6 AND data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2) OR (rom_base_bank_5 AND NOT data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2 AND data_0_cmp_eq0002/data_0_cmp_eq0002_D2)); data(5) <= data_I(5) when data_OE(5) = '1' else 'Z'; data_OE(5) <= data_0_or0000/data_0_or0000_D2; data_I(6) <= (rom_base_bank_6 AND NOT data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2 AND data_0_cmp_eq0002/data_0_cmp_eq0002_D2); data(6) <= data_I(6) when data_OE(6) = '1' else 'Z'; data_OE(6) <= data_0_or0000/data_0_or0000_D2; data_I(7) <= NOT (((NOT i2c_data_pin.PIN AND $OpTx$FX_DC$475 AND NOT check_1050_6810_access_cmp_eq0000/check_1050_6810_access_cmp_eq0000_D2 AND i2c_clk_and0000/i2c_clk_and0000_D2) OR (adr(12) AND rw AND NOT adr(11) AND NOT centronics_busy AND check_1050_6810_access_cmp_eq0000/check_1050_6810_access_cmp_eq0000_D2) OR (rom_bank_c000_enable(0) AND $OpTx$FX_DC$475 AND data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT check_1050_6810_access_cmp_eq0000/check_1050_6810_access_cmp_eq0000_D2 AND NOT i2c_clk_and0000/i2c_clk_and0000_D2) OR (NOT d7_ram_rom.PIN AND NOT data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0002/data_0_cmp_eq0002_D2 AND NOT check_1050_6810_access_cmp_eq0000/check_1050_6810_access_cmp_eq0000_D2 AND NOT i2c_clk_and0000/i2c_clk_and0000_D2) OR (NOT rom_source_is_ram AND $OpTx$FX_DC$475 AND NOT data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND data_0_cmp_eq0002/data_0_cmp_eq0002_D2 AND NOT check_1050_6810_access_cmp_eq0000/check_1050_6810_access_cmp_eq0000_D2 AND NOT i2c_clk_and0000/i2c_clk_and0000_D2) OR (adr(4) AND adr(3) AND NOT adr(0) AND adr(12) AND adr(13) AND adr(14) AND NOT adr(15) AND NOT adr(9) AND NOT adr(7) AND NOT adr(10) AND NOT adr(5) AND NOT adr(1) AND NOT adr(2) AND NOT adr(11) AND NOT adr(6) AND NOT adr(8) AND $OpTx$FX_DC$475 AND NOT check_1050_6810_access_cmp_eq0000/check_1050_6810_access_cmp_eq0000_D2) OR (adr(4) AND NOT adr(3) AND adr(0) AND adr(12) AND adr(13) AND adr(14) AND NOT adr(15) AND NOT adr(9) AND NOT adr(7) AND NOT adr(10) AND NOT adr(5) AND NOT adr(1) AND NOT adr(2) AND NOT adr(11) AND NOT adr(6) AND NOT adr(8) AND $OpTx$FX_DC$475 AND NOT data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0002/data_0_cmp_eq0002_D2 AND NOT check_1050_6810_access_cmp_eq0000/check_1050_6810_access_cmp_eq0000_D2 AND NOT i2c_clk_and0000/i2c_clk_and0000_D2) OR (NOT adr(12) AND NOT d7_ram_rom.PIN AND check_1050_6810_access_cmp_eq0000/check_1050_6810_access_cmp_eq0000_D2) OR (NOT rw AND NOT d7_ram_rom.PIN AND check_1050_6810_access_cmp_eq0000/check_1050_6810_access_cmp_eq0000_D2) OR (NOT d7_ram_rom.PIN AND adr(11) AND check_1050_6810_access_cmp_eq0000/check_1050_6810_access_cmp_eq0000_D2) OR (NOT d7_ram_rom.PIN AND NOT $OpTx$FX_DC$475 AND NOT check_1050_6810_access_cmp_eq0000/check_1050_6810_access_cmp_eq0000_D2))); data(7) <= data_I(7) when data_OE(7) = '1' else 'Z'; data_OE(7) <= data_7_or0005/data_7_or0005_D2; data_0_cmp_eq0000/data_0_cmp_eq0000_D2 <= (adr(4) AND adr(3) AND NOT adr(0) AND adr(12) AND adr(13) AND adr(14) AND NOT adr(15) AND NOT adr(9) AND NOT adr(7) AND NOT adr(10) AND NOT adr(5) AND NOT adr(1) AND NOT adr(2) AND NOT adr(11) AND NOT adr(6) AND NOT adr(8)); data_0_cmp_eq0001/data_0_cmp_eq0001_D2 <= (NOT adr(4) AND NOT adr(3) AND NOT adr(0) AND adr(12) AND adr(13) AND adr(14) AND NOT adr(15) AND NOT adr(9) AND NOT adr(7) AND NOT adr(10) AND NOT adr(5) AND NOT adr(1) AND NOT adr(2) AND NOT adr(11) AND NOT adr(6) AND NOT adr(8)); data_0_cmp_eq0002/data_0_cmp_eq0002_D2 <= (adr(4) AND NOT adr(3) AND NOT adr(0) AND adr(12) AND adr(13) AND adr(14) AND NOT adr(15) AND NOT adr(9) AND NOT adr(7) AND NOT adr(10) AND NOT adr(5) AND NOT adr(1) AND NOT adr(2) AND NOT adr(11) AND NOT adr(6) AND NOT adr(8)); data_0_or0000/data_0_or0000_D2 <= ((phi2 AND rw AND $OpTx$FX_DC$475 AND NOT $OpTx$FX_SC$508) OR (adr(4) AND NOT adr(3) AND adr(0) AND adr(12) AND phi2 AND adr(13) AND adr(14) AND rw AND NOT adr(15) AND NOT adr(9) AND NOT adr(7) AND NOT adr(10) AND NOT adr(5) AND NOT adr(1) AND NOT adr(2) AND NOT adr(11) AND NOT adr(6) AND NOT adr(8) AND $OpTx$FX_DC$475)); data_7_or0005/data_7_or0005_D2 <= ((phi2 AND rw AND NOT $OpTx$FX_DC$501) OR (adr(12) AND phi2 AND rw AND NOT adr(11) AND check_1050_6810_access_cmp_eq0000/check_1050_6810_access_cmp_eq0000_D2) OR (phi2 AND rw AND $OpTx$FX_DC$475 AND NOT $OpTx$FX_SC$508 AND NOT check_1050_6810_access_cmp_eq0000/check_1050_6810_access_cmp_eq0000_D2) OR (NOT adr(4) AND NOT adr(3) AND adr(12) AND phi2 AND adr(13) AND adr(14) AND rw AND NOT adr(15) AND NOT adr(9) AND NOT adr(7) AND NOT adr(10) AND adr(5) AND NOT adr(2) AND NOT adr(11) AND NOT adr(6) AND NOT adr(8) AND $OpTx$FX_DC$475) OR (adr(4) AND NOT adr(3) AND adr(0) AND adr(12) AND phi2 AND adr(13) AND adr(14) AND rw AND NOT adr(15) AND NOT adr(9) AND NOT adr(7) AND NOT adr(10) AND NOT adr(5) AND NOT adr(1) AND NOT adr(2) AND NOT adr(11) AND NOT adr(6) AND NOT adr(8) AND $OpTx$FX_DC$475)); FDCPE_density0: FDCPE port map (density(0),density_D(0),NOT phi2,'0','0'); density_D(0) <= ((NOT reset) OR (density(0) AND NOT $OpTx$FX_DC$492) OR (NOT adr(0) AND NOT floppy_mode(3) AND adr(14) AND NOT rw AND NOT adr(15) AND adr(1) AND NOT data(0).PIN AND $OpTx$FX_DC$461) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND data(6).PIN) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND data(7).PIN)); FDCPE_density1: FDCPE port map (density(1),density_D(1),NOT phi2,'0','0'); density_D(1) <= ((NOT reset) OR (density(1) AND NOT $OpTx$FX_DC$492) OR (NOT adr(0) AND NOT floppy_mode(3) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(1).PIN AND adr(1) AND $OpTx$FX_DC$461) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(7).PIN)); FDCPE_density2: FDCPE port map (density(2),density_D(2),NOT phi2,'0','0'); density_D(2) <= ((NOT reset) OR (density(2) AND NOT $OpTx$FX_DC$492) OR (NOT adr(0) AND NOT floppy_mode(3) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(2).PIN AND adr(1) AND $OpTx$FX_DC$461) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(6).PIN)); fdc_write_out <= ((archiver_a11 AND fdc_write_in) OR (fdc_write_in AND NOT riot_ready_in_IBUF$BUF0/riot_ready_in_IBUF$BUF0_TRST)); FDCPE_floppy_mode0: FDCPE port map (floppy_mode(0),floppy_mode_D(0),NOT phi2,'0','0'); floppy_mode_D(0) <= ((floppy_mode(0) AND NOT floppy_mode_0__or0000/floppy_mode_0__or0000_D2) OR (data(0).PIN AND reset AND floppy_mode_0__or0000/floppy_mode_0__or0000_D2)); FDCPE_floppy_mode1: FDCPE port map (floppy_mode(1),floppy_mode_D(1),NOT phi2,'0','0'); floppy_mode_D(1) <= ((floppy_mode(1) AND NOT floppy_mode_0__or0000/floppy_mode_0__or0000_D2) OR (data(1).PIN AND reset AND floppy_mode_0__or0000/floppy_mode_0__or0000_D2)); FDCPE_floppy_mode2: FDCPE port map (floppy_mode(2),floppy_mode_D(2),NOT phi2,'0','0'); floppy_mode_D(2) <= ((floppy_mode(2) AND NOT floppy_mode_0__or0000/floppy_mode_0__or0000_D2) OR (data(2).PIN AND reset AND floppy_mode_0__or0000/floppy_mode_0__or0000_D2)); FDCPE_floppy_mode3: FDCPE port map (floppy_mode(3),floppy_mode_D(3),NOT phi2,'0','0'); floppy_mode_D(3) <= ((floppy_mode(3) AND NOT floppy_mode_0__or0000/floppy_mode_0__or0000_D2) OR (data(3).PIN AND reset AND floppy_mode_0__or0000/floppy_mode_0__or0000_D2)); floppy_mode_0__or0000/floppy_mode_0__or0000_D2 <= ((NOT reset) OR (adr(4) AND NOT adr(3) AND adr(0) AND adr(12) AND adr(13) AND adr(14) AND NOT adr(15) AND NOT adr(9) AND NOT adr(7) AND NOT adr(10) AND NOT adr(5) AND NOT adr(1) AND NOT adr(2) AND NOT adr(11) AND NOT adr(6) AND NOT adr(8) AND $OpTx$FX_DC$475)); FTCPE_happy_a12: FTCPE port map (happy_a12,happy_a12_T,NOT phi2,'0','0'); happy_a12_T <= ((NOT happy_a12 AND NOT reset AND happy_a12__or0001/happy_a12__or0001_D2) OR (adr(3) AND adr(0) AND NOT happy_a12 AND NOT adr(1) AND NOT adr(2) AND happy_a12__or0001/happy_a12__or0001_D2) OR (adr(3) AND NOT adr(0) AND happy_a12 AND NOT adr(1) AND NOT adr(2) AND reset AND happy_a12__or0001/happy_a12__or0001_D2)); happy_a12__or0001/happy_a12__or0001_D2 <= ((NOT reset) OR (adr(4) AND NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND adr(15) AND adr(9) AND adr(7) AND adr(10) AND adr(5) AND adr(11) AND adr(6) AND adr(8))); FTCPE_i2c_clk: FTCPE port map (i2c_clk,i2c_clk_T,NOT phi2,'0','0'); i2c_clk_T <= ((adr(0) AND NOT rw AND NOT i2c_clk AND $OpTx$FX_DC$475 AND i2c_clk_and0000/i2c_clk_and0000_D2) OR (NOT adr(0) AND NOT rw AND i2c_clk AND reset AND $OpTx$FX_DC$475 AND i2c_clk_and0000/i2c_clk_and0000_D2) OR (NOT i2c_clk AND NOT reset)); i2c_clk_and0000/i2c_clk_and0000_D2 <= (NOT adr(4) AND NOT adr(3) AND adr(12) AND adr(13) AND adr(14) AND NOT adr(15) AND NOT adr(9) AND NOT adr(7) AND NOT adr(10) AND adr(5) AND NOT adr(2) AND NOT adr(11) AND NOT adr(6) AND NOT adr(8)); i2c_clk_pin_I <= '0'; i2c_clk_pin <= i2c_clk_pin_I when i2c_clk_pin_OE = '1' else 'Z'; i2c_clk_pin_OE <= NOT i2c_clk; FTCPE_i2c_data: FTCPE port map (i2c_data,i2c_data_T,NOT phi2,'0','0'); i2c_data_T <= ((NOT i2c_data AND NOT reset) OR (NOT rw AND NOT i2c_data AND adr(1) AND $OpTx$FX_DC$475 AND i2c_clk_and0000/i2c_clk_and0000_D2) OR (NOT rw AND i2c_data AND NOT adr(1) AND reset AND $OpTx$FX_DC$475 AND i2c_clk_and0000/i2c_clk_and0000_D2)); i2c_data_pin_I <= '0'; i2c_data_pin <= i2c_data_pin_I when i2c_data_pin_OE = '1' else 'Z'; i2c_data_pin_OE <= NOT i2c_data; io_1050 <= NOT (((NOT adr(12) AND floppy_mode(3) AND floppy_mode(0) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND adr(10)) OR (NOT adr(12) AND floppy_mode(3) AND floppy_mode(0) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND adr(7) AND NOT adr(11)) OR (adr(9) AND check_1050_6810_access_mux0001/check_1050_6810_access_mux0001_D2) OR (adr(7) AND check_1050_6810_access_mux0001/check_1050_6810_access_mux0001_D2) OR (adr(10) AND check_1050_6810_access_mux0001/check_1050_6810_access_mux0001_D2) OR (NOT adr(12) AND NOT floppy_mode(3) AND floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(7)) OR (NOT adr(12) AND NOT floppy_mode(3) AND floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(10)))); FDCPE_ram_bank_0: FDCPE port map (ram_bank_0,ram_bank_0_D,NOT phi2,'0','0'); ram_bank_0_D <= ((data(0).PIN AND $OpTx$FX_SC$520) OR (reset AND ram_bank_0 AND NOT N27/N27_D2)); FDCPE_ram_bank_1: FDCPE port map (ram_bank_1,ram_bank_1_D,NOT phi2,'0','0'); ram_bank_1_D <= ((data(1).PIN AND $OpTx$FX_SC$520) OR (reset AND ram_bank_1 AND NOT N27/N27_D2)); FDCPE_ram_bank_2: FDCPE port map (ram_bank_2,ram_bank_2_D,NOT phi2,'0','0'); ram_bank_2_D <= ((data(2).PIN AND $OpTx$FX_SC$520) OR (reset AND ram_bank_2 AND NOT N27/N27_D2)); FDCPE_ram_bank_3: FDCPE port map (ram_bank_3,ram_bank_3_D,NOT phi2,'0','0'); ram_bank_3_D <= ((data(3).PIN AND $OpTx$FX_SC$520) OR (reset AND ram_bank_3 AND NOT N27/N27_D2)); FDCPE_ram_bank_4: FDCPE port map (ram_bank_4,ram_bank_4_D,NOT phi2,'0','0'); ram_bank_4_D <= ((data(4).PIN AND $OpTx$FX_SC$520) OR (reset AND ram_bank_4 AND NOT N27/N27_D2)); FDCPE_ram_bank_5: FDCPE port map (ram_bank_5,ram_bank_5_D,NOT phi2,'0','0'); ram_bank_5_D <= ((reset AND ram_bank_5 AND NOT N27/N27_D2) OR (NOT adr(12) AND adr(13) AND adr(14) AND NOT rw AND NOT adr(15) AND data(5).PIN AND reset AND $OpTx$FX_DC$475)); ram_ce <= NOT ((($OpTx$FX_DC$556) OR ($OpTx$FX_DC$502) OR (i2c_clk.EXP) OR (adr(12) AND NOT floppy_mode(3) AND floppy_mode(0) AND floppy_mode(2) AND rom_source_is_ram AND rw) OR (NOT floppy_mode(3) AND floppy_mode(0) AND NOT floppy_mode(2) AND floppy_mode(1) AND NOT adr(14) AND adr(15)) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND NOT adr(14) AND adr(15)) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND floppy_mode(1) AND NOT adr(14) AND adr(15) AND NOT ram_bank_4) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND rom_source_is_ram AND adr(13) AND adr(14) AND rw AND adr(15)) OR (adr(12) AND floppy_mode(3) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND rom_source_is_ram AND rw) OR (adr(12) AND NOT floppy_mode(3) AND floppy_mode(2) AND NOT floppy_mode(1) AND rom_source_is_ram AND rw) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND floppy_mode(1) AND NOT adr(14) AND adr(15) AND NOT ram_bank_3))); ram_rom_adr(8) <= ((adr(9) AND NOT N104/N104_D2 AND $OpTx$FX_DC$515) OR (adr(8) AND NOT N104/N104_D2 AND NOT $OpTx$FX_DC$515)); ram_rom_adr(9) <= NOT ((NOT adr(9) AND NOT N104/N104_D2 AND NOT $OpTx$FX_DC$515)); ram_rom_adr(10) <= ((adr(10)) OR (N104/N104_D2) OR (NOT adr(12) AND NOT floppy_mode(3) AND floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND NOT adr(7))); ram_rom_adr(11) <= NOT (((adr(12) AND floppy_mode(3) AND NOT floppy_mode(0) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND NOT rw AND NOT N104/N104_D2 AND NOT $OpTx$FX_DC$515) OR (adr(12) AND NOT floppy_mode(3) AND floppy_mode(0) AND floppy_mode(2) AND NOT floppy_mode(1) AND NOT turbo_rom_adr(11) AND NOT N104/N104_D2 AND NOT $OpTx$FX_DC$515) OR (adr(12) AND floppy_mode(3) AND NOT floppy_mode(0) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND NOT archiver_a11 AND NOT N104/N104_D2 AND NOT $OpTx$FX_DC$515) OR (NOT adr(12) AND floppy_mode(3) AND floppy_mode(0) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND NOT adr(10) AND NOT N104/N104_D2 AND NOT $OpTx$FX_DC$515) OR (NOT adr(12) AND NOT adr(11) AND NOT N104/N104_D2 AND NOT $OpTx$FX_DC$515) OR (floppy_mode(3) AND NOT adr(11) AND NOT N104/N104_D2 AND NOT $OpTx$FX_DC$515) OR (NOT floppy_mode(0) AND NOT adr(11) AND NOT N104/N104_D2 AND NOT $OpTx$FX_DC$515) OR (NOT floppy_mode(2) AND NOT adr(11) AND NOT N104/N104_D2 AND NOT $OpTx$FX_DC$515) OR (floppy_mode(1) AND NOT adr(11) AND NOT N104/N104_D2 AND NOT $OpTx$FX_DC$515))); ram_rom_adr(12) <= (($OpTx$FX_DC$556.EXP) OR (NOT adr(12) AND floppy_mode(2) AND NOT floppy_mode(1) AND NOT rom_source_is_ram AND rom_base_bank_0) OR (floppy_mode(3) AND floppy_mode(0) AND NOT rom_source_is_ram AND rom_base_bank_0 AND NOT adr(11)) OR (floppy_mode(3) AND floppy_mode(1) AND NOT rom_source_is_ram AND NOT adr(13) AND rom_base_bank_0) OR (floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND NOT rom_source_is_ram AND rom_base_bank_0) OR (floppy_mode(2) AND floppy_mode(1) AND NOT rom_source_is_ram AND NOT adr(15) AND rom_base_bank_0) OR (N104/N104_D2) OR ($OpTx$FX_DC$515) OR (i2c_clk_and0000/i2c_clk_and0000_D2.EXP) OR (adr(12) AND NOT floppy_mode(3) AND NOT floppy_mode(2)) OR (floppy_mode(3) AND floppy_mode(2) AND NOT rom_source_is_ram AND rom_base_bank_0) OR (NOT floppy_mode(0) AND floppy_mode(2) AND NOT floppy_mode(1) AND NOT rom_source_is_ram AND rom_base_bank_0) OR (adr(12) AND floppy_mode(3) AND floppy_mode(0) AND NOT rom_source_is_ram AND rom_base_bank_0) OR (floppy_mode(3) AND floppy_mode(0) AND NOT rom_source_is_ram AND adr(10) AND rom_base_bank_0) OR (adr(12) AND floppy_mode(3) AND NOT rom_source_is_ram AND rw AND rom_base_bank_0 AND adr(11)) OR (floppy_mode(3) AND floppy_mode(1) AND NOT rom_source_is_ram AND adr(14) AND NOT adr(15) AND rom_base_bank_0) OR (floppy_mode(3) AND floppy_mode(1) AND NOT rom_source_is_ram AND NOT adr(14) AND adr(15) AND rom_base_bank_0)); ram_rom_adr(13) <= ((adr(12) AND floppy_mode(3) AND NOT floppy_mode(0) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND NOT rw AND NOT N104/N104_D2) OR (adr(12) AND floppy_mode(3) AND NOT floppy_mode(0) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND NOT adr(11) AND NOT N104/N104_D2) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND adr(14) AND adr(15) AND rom_bank_c000_0 AND $OpTx$FX_DC$475 AND NOT N104/N104_D2) OR (NOT floppy_mode(0) AND NOT floppy_mode(2) AND floppy_mode(1) AND adr(13) AND NOT adr(14) AND NOT adr(15) AND NOT N104/N104_D2) OR (NOT N104/N104_D2 AND $OpTx$FX_DC$502) OR (NOT rom_source_is_ram AND rom_base_bank_1 AND NOT N104/N104_D2 AND NOT $OpTx$FX_DC$531) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND adr(13) AND adr(14) AND NOT N104/N104_D2) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND adr(13) AND NOT adr(15) AND NOT N104/N104_D2) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT adr(14) AND adr(15) AND ram_bank_0 AND NOT N104/N104_D2)); ram_rom_adr(14) <= (($OpTx$FX_DC$556) OR ($OpTx$FX_DC$502) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT adr(15) AND $OpTx$FX_DC$475) OR (NOT rom_source_is_ram AND adr(14) AND rom_base_bank_2 AND NOT $OpTx$FX_DC$475) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND adr(13) AND adr(14) AND $OpTx$FX_DC$475) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT adr(13) AND rom_bank_c000_1 AND $OpTx$FX_DC$475) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT adr(14) AND adr(15) AND ram_bank_1) OR (floppy_mode(3) AND NOT rom_source_is_ram AND rom_base_bank_2) OR (floppy_mode(2) AND NOT rom_source_is_ram AND rom_base_bank_2) OR (NOT rom_source_is_ram AND NOT adr(15) AND rom_base_bank_2)); ram_rom_adr(15) <= ((rom_source_is_ram AND NOT N104/N104_D2 AND NOT $OpTx$FX_DC$554) OR (rom_base_bank_3 AND NOT N104/N104_D2 AND NOT $OpTx$FX_DC$554) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND adr(13) AND NOT adr(14) AND adr(15) AND ram_bank_2 AND NOT N104/N104_D2) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND rom_bank_c000_enable(0) AND NOT adr(13) AND adr(14) AND adr(15) AND rom_bank_c000_2 AND $OpTx$FX_DC$475 AND NOT N104/N104_D2)); ram_rom_adr(16) <= ((NOT $OpTx$FX_DC$517) OR (rom_base_bank_4 AND NOT N64/N64_D2) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT adr(14) AND adr(15) AND ram_bank_3) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND rom_bank_c000_enable(0) AND NOT adr(13) AND adr(15) AND rom_bank_c000_3 AND $OpTx$FX_DC$475)); ram_rom_adr(17) <= ((NOT $OpTx$FX_DC$517) OR (rom_base_bank_5 AND NOT N64/N64_D2) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT adr(14) AND adr(15) AND ram_bank_4) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND rom_bank_c000_enable(0) AND NOT adr(13) AND adr(15) AND rom_bank_c000_4 AND $OpTx$FX_DC$475)); ram_rom_adr(18) <= ((NOT $OpTx$FX_DC$517) OR (NOT floppy_mode(3) AND floppy_mode(0) AND NOT floppy_mode(2) AND NOT adr(14) AND adr(15) AND ram_bank_5) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND rom_bank_c000_enable(0) AND NOT adr(13) AND adr(15) AND rom_bank_c000_5 AND $OpTx$FX_DC$475) OR (rom_base_bank_6 AND NOT N64/N64_D2) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND NOT adr(14) AND adr(15) AND ram_bank_5)); ram_rom_oe <= NOT ((phi2 AND rw)); ram_rom_we <= NOT ((phi2 AND NOT rw)); FDCPE_reset: FDCPE port map (reset,reset_sync,NOT phi2,'0','0'); FDCPE_reset_sync: FDCPE port map (reset_sync,reset_in,NOT phi2,'0','0'); riot_ready_in_IBUF$BUF0/riot_ready_in_IBUF$BUF0_TRST <= (floppy_mode(3) AND NOT floppy_mode(0) AND NOT floppy_mode(2) AND NOT floppy_mode(1)); riot_ready_inout_I <= riot_ready_in; riot_ready_inout <= riot_ready_inout_I when riot_ready_inout_OE = '1' else 'Z'; riot_ready_inout_OE <= NOT ((floppy_mode(3) AND NOT floppy_mode(0) AND NOT floppy_mode(2) AND NOT floppy_mode(1))); FDCPE_rom_bank_c000_0: FDCPE port map (rom_bank_c000_0,rom_bank_c000_0_D,NOT phi2,'0','0'); rom_bank_c000_0_D <= ((rom_bank_c000_0 AND NOT rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2) OR (data(0).PIN AND reset AND rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2)); rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2 <= ((NOT reset) OR (NOT rw AND $OpTx$FX_DC$475 AND data_0_cmp_eq0001/data_0_cmp_eq0001_D2)); FDCPE_rom_bank_c000_1: FDCPE port map (rom_bank_c000_1,rom_bank_c000_1_D,NOT phi2,'0','0'); rom_bank_c000_1_D <= ((NOT rom_bank_c000_1 AND NOT rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2) OR (NOT data(1).PIN AND reset AND rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2)); FDCPE_rom_bank_c000_2: FDCPE port map (rom_bank_c000_2,rom_bank_c000_2_D,NOT phi2,'0','0'); rom_bank_c000_2_D <= ((rom_bank_c000_2 AND NOT rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2) OR (data(2).PIN AND reset AND rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2)); FDCPE_rom_bank_c000_3: FDCPE port map (rom_bank_c000_3,rom_bank_c000_3_D,NOT phi2,'0','0'); rom_bank_c000_3_D <= ((rom_bank_c000_3 AND NOT rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2) OR (data(3).PIN AND reset AND rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2)); FDCPE_rom_bank_c000_4: FDCPE port map (rom_bank_c000_4,rom_bank_c000_4_D,NOT phi2,'0','0'); rom_bank_c000_4_D <= ((rom_bank_c000_4 AND NOT rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2) OR (reset AND data(4).PIN AND rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2)); FDCPE_rom_bank_c000_5: FDCPE port map (rom_bank_c000_5,rom_bank_c000_5_D,NOT phi2,'0','0'); rom_bank_c000_5_D <= ((rom_bank_c000_5 AND NOT rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2) OR (data(5).PIN AND reset AND rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2)); FDCPE_rom_bank_c000_enable0: FDCPE port map (rom_bank_c000_enable(0),rom_bank_c000_enable_D(0),NOT phi2,'0','0'); rom_bank_c000_enable_D(0) <= ((rom_bank_c000_enable(0) AND NOT rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2) OR (NOT data(7).PIN AND reset AND rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2)); FDCPE_rom_base_bank_0: FDCPE port map (rom_base_bank_0,rom_base_bank_0_D,NOT phi2,'0','0'); rom_base_bank_0_D <= ((rom_base_bank_0 AND NOT rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2) OR (data(0).PIN AND reset AND rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2)); rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2 <= ((NOT reset) OR ($OpTx$FX_DC$475 AND data_0_cmp_eq0002/data_0_cmp_eq0002_D2)); FDCPE_rom_base_bank_1: FDCPE port map (rom_base_bank_1,rom_base_bank_1_D,NOT phi2,'0','0'); rom_base_bank_1_D <= ((rom_base_bank_1 AND NOT rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2) OR (data(1).PIN AND reset AND rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2)); FDCPE_rom_base_bank_2: FDCPE port map (rom_base_bank_2,rom_base_bank_2_D,NOT phi2,'0','0'); rom_base_bank_2_D <= ((rom_base_bank_2 AND NOT rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2) OR (data(2).PIN AND reset AND rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2)); FDCPE_rom_base_bank_3: FDCPE port map (rom_base_bank_3,rom_base_bank_3_D,NOT phi2,'0','0'); rom_base_bank_3_D <= ((NOT rom_base_bank_3 AND NOT rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2) OR (NOT data(3).PIN AND reset AND rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2)); FDCPE_rom_base_bank_4: FDCPE port map (rom_base_bank_4,rom_base_bank_4_D,NOT phi2,'0','0'); rom_base_bank_4_D <= ((NOT rom_base_bank_4 AND NOT rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2) OR (reset AND NOT data(4).PIN AND rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2)); FDCPE_rom_base_bank_5: FDCPE port map (rom_base_bank_5,rom_base_bank_5_D,NOT phi2,'0','0'); rom_base_bank_5_D <= ((NOT rom_base_bank_5 AND NOT rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2) OR (NOT data(5).PIN AND reset AND rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2)); FDCPE_rom_base_bank_6: FDCPE port map (rom_base_bank_6,rom_base_bank_6_D,NOT phi2,'0','0'); rom_base_bank_6_D <= ((NOT rom_base_bank_6 AND NOT rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2) OR (NOT data(6).PIN AND reset AND rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2)); rom_ce <= NOT (((NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(1) AND NOT rom_source_is_ram AND adr(14) AND rw AND adr(15)) OR (NOT floppy_mode(3) AND floppy_mode(0) AND NOT floppy_mode(2) AND floppy_mode(1) AND rom_bank_c000_enable(0) AND NOT adr(13) AND adr(14) AND adr(15)) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND rom_bank_c000_enable(0) AND NOT adr(13) AND adr(14) AND adr(15)) OR (NOT floppy_mode(0) AND NOT floppy_mode(2) AND floppy_mode(1) AND NOT rom_source_is_ram AND adr(13) AND adr(14) AND rw AND adr(15)) OR (adr(12) AND NOT floppy_mode(3) AND floppy_mode(0) AND floppy_mode(2) AND NOT rom_source_is_ram AND rw) OR (adr(12) AND NOT floppy_mode(3) AND floppy_mode(2) AND NOT floppy_mode(1) AND NOT rom_source_is_ram AND rw) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT rom_source_is_ram AND adr(14) AND rw AND adr(15)) OR (adr(12) AND floppy_mode(3) AND floppy_mode(0) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND NOT rom_source_is_ram AND rw) OR (adr(12) AND floppy_mode(3) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND NOT rom_source_is_ram AND rw AND adr(11)))); FDCPE_rom_source_is_ram: FDCPE port map (rom_source_is_ram,rom_source_is_ram_D,NOT phi2,'0','0'); rom_source_is_ram_D <= ((rom_source_is_ram AND NOT rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2) OR (data(7).PIN AND reset AND rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2)); FTCPE_summer: FTCPE port map (summer,summer_T,NOT phi2,'0','0'); summer_T <= ((adr(0) AND NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT adr(13) AND adr(14) AND NOT rw AND NOT adr(15) AND adr(1) AND reset) OR (adr(0) AND NOT floppy_mode(3) AND floppy_mode(0) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND adr(1) AND reset)); FDCPE_track_hi0: FDCPE port map (track_hi(0),track_hi_D(0),NOT phi2,'0','0'); track_hi_D(0) <= ((NOT reset) OR (track_hi(0) AND NOT N2/N2_D2) OR (adr(0) AND NOT floppy_mode(3) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT adr(1) AND NOT data(0).PIN AND $OpTx$FX_DC$461) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(5).PIN AND data(4).PIN)); FDCPE_track_hi1: FDCPE port map (track_hi(1),track_hi_D(1),NOT phi2,'0','0'); track_hi_D(1) <= ((NOT reset) OR (track_hi(1) AND NOT N2/N2_D2) OR (adr(0) AND NOT floppy_mode(3) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(1).PIN AND NOT adr(1) AND $OpTx$FX_DC$461)); FDCPE_track_hi2: FDCPE port map (track_hi(2),track_hi_D(2),NOT phi2,'0','0'); track_hi_D(2) <= ((NOT reset) OR (track_hi(2) AND NOT N2/N2_D2) OR (adr(0) AND NOT floppy_mode(3) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(2).PIN AND NOT adr(1) AND $OpTx$FX_DC$461) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND data(5).PIN AND NOT data(4).PIN)); FDCPE_track_hi3: FDCPE port map (track_hi(3),track_hi_D(3),NOT phi2,'0','0'); track_hi_D(3) <= ((NOT reset) OR (track_hi(3) AND NOT N2/N2_D2) OR (adr(0) AND NOT floppy_mode(3) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(3).PIN AND NOT adr(1) AND $OpTx$FX_DC$461) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(5).PIN AND data(4).PIN)); FDCPE_track_hi4: FDCPE port map (track_hi(4),track_hi_D(4),NOT phi2,'0','0'); track_hi_D(4) <= ((NOT reset) OR (track_hi(4) AND NOT N2/N2_D2) OR (adr(0) AND NOT floppy_mode(3) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT adr(1) AND NOT data(4).PIN AND $OpTx$FX_DC$461) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND data(4).PIN)); FDCPE_track_hi5: FDCPE port map (track_hi(5),track_hi_D(5),NOT phi2,'0','0'); track_hi_D(5) <= ((NOT reset) OR (track_hi(5) AND NOT N2/N2_D2) OR (adr(0) AND NOT floppy_mode(3) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT adr(1) AND NOT data(5).PIN AND $OpTx$FX_DC$461) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND data(5).PIN) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND data(4).PIN)); FDCPE_track_hi6: FDCPE port map (track_hi(6),track_hi_D(6),NOT phi2,'0','0'); track_hi_D(6) <= ((NOT reset) OR (track_hi(6) AND NOT N2/N2_D2) OR (adr(0) AND NOT floppy_mode(3) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT adr(1) AND NOT data(6).PIN AND $OpTx$FX_DC$461) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(5).PIN)); FDCPE_track_lo0: FDCPE port map (track_lo(0),track_lo_D(0),NOT phi2,'0','0'); track_lo_D(0) <= ((NOT reset) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(1).PIN AND NOT data(3).PIN AND data(2).PIN AND NOT data(0).PIN) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(1).PIN AND NOT data(3).PIN AND NOT data(2).PIN AND data(0).PIN) OR (track_lo(0) AND NOT N11/N11_D2) OR (NOT adr(0) AND NOT floppy_mode(3) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT adr(1) AND NOT data(0).PIN AND $OpTx$FX_DC$461) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND data(1).PIN AND data(3).PIN AND NOT data(2).PIN AND data(0).PIN) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(1).PIN AND data(3).PIN AND data(2).PIN AND data(0).PIN)); FDCPE_track_lo1: FDCPE port map (track_lo(1),track_lo_D(1),NOT phi2,'0','0'); track_lo_D(1) <= ((NOT reset) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND data(3).PIN AND data(2).PIN AND NOT data(0).PIN) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(1).PIN AND NOT data(3).PIN AND data(2).PIN AND data(0).PIN) OR (track_lo(1) AND NOT N11/N11_D2) OR (NOT adr(0) AND NOT floppy_mode(3) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(1).PIN AND NOT adr(1) AND $OpTx$FX_DC$461) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND data(1).PIN AND data(3).PIN AND data(0).PIN) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND data(1).PIN AND data(2).PIN AND NOT data(0).PIN)); FDCPE_track_lo2: FDCPE port map (track_lo(2),track_lo_D(2),NOT phi2,'0','0'); track_lo_D(2) <= ((NOT reset) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND data(1).PIN AND NOT data(3).PIN AND NOT data(2).PIN AND NOT data(0).PIN) OR (track_lo(2) AND NOT N11/N11_D2) OR (NOT adr(0) AND NOT floppy_mode(3) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(2).PIN AND NOT adr(1) AND $OpTx$FX_DC$461) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND data(1).PIN AND data(3).PIN AND data(2).PIN) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND data(3).PIN AND data(2).PIN AND NOT data(0).PIN)); FDCPE_track_lo3: FDCPE port map (track_lo(3),track_lo_D(3),NOT phi2,'0','0'); track_lo_D(3) <= ((NOT reset) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(1).PIN AND NOT data(3).PIN AND data(2).PIN AND NOT data(0).PIN) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND data(1).PIN AND data(3).PIN AND NOT data(2).PIN AND NOT data(0).PIN) OR (track_lo(3) AND NOT N11/N11_D2) OR (NOT adr(0) AND NOT floppy_mode(3) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(3).PIN AND NOT adr(1) AND $OpTx$FX_DC$461) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND data(1).PIN AND data(2).PIN AND data(0).PIN) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(1).PIN AND NOT data(3).PIN AND NOT data(2).PIN AND data(0).PIN)); FDCPE_track_lo4: FDCPE port map (track_lo(4),track_lo_D(4),NOT phi2,'0','0'); track_lo_D(4) <= ((NOT reset) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(1).PIN AND NOT data(2).PIN AND data(0).PIN) OR (track_lo(4) AND NOT N11/N11_D2) OR (NOT adr(0) AND NOT floppy_mode(3) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT adr(1) AND NOT data(4).PIN AND $OpTx$FX_DC$461) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(3).PIN AND data(0).PIN) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(1).PIN AND NOT data(3).PIN AND data(2).PIN)); FDCPE_track_lo5: FDCPE port map (track_lo(5),track_lo_D(5),NOT phi2,'0','0'); track_lo_D(5) <= ((NOT reset) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(3).PIN AND NOT data(2).PIN AND data(0).PIN) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(1).PIN AND data(3).PIN AND data(2).PIN AND data(0).PIN) OR (track_lo(5) AND NOT N11/N11_D2) OR (NOT adr(0) AND NOT floppy_mode(3) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT adr(1) AND NOT data(5).PIN AND $OpTx$FX_DC$461) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND data(1).PIN AND NOT data(3).PIN AND NOT data(2).PIN) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND data(1).PIN AND NOT data(3).PIN AND data(0).PIN)); FDCPE_track_lo6: FDCPE port map (track_lo(6),track_lo_D(6),NOT phi2,'0','0'); track_lo_D(6) <= ((NOT reset) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(1).PIN AND NOT data(3).PIN AND NOT data(2).PIN) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND data(1).PIN AND NOT data(3).PIN AND data(2).PIN AND data(0).PIN) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(1).PIN AND data(3).PIN AND data(2).PIN AND NOT data(0).PIN) OR (track_lo(6) AND NOT N11/N11_D2) OR (NOT adr(0) AND NOT floppy_mode(3) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT adr(1) AND NOT data(6).PIN AND $OpTx$FX_DC$461)); turbo_centronics_clk__or0001/turbo_centronics_clk__or0001_D2 <= ((NOT reset) OR (adr(12) AND NOT adr(11) AND check_1050_6810_access_cmp_eq0000/check_1050_6810_access_cmp_eq0000_D2)); FDCPE_turbo_rom_adr11: FDCPE port map (turbo_rom_adr(11),turbo_rom_adr_D(11),NOT phi2,'0','0'); turbo_rom_adr_D(11) <= ((NOT turbo_rom_adr(11) AND NOT turbo_rom_adr_11__or0001/turbo_rom_adr_11__or0001_D2) OR (NOT data(6).PIN AND reset AND NOT data(4).PIN AND turbo_rom_adr_11__or0001/turbo_rom_adr_11__or0001_D2)); FDCPE_turbo_rom_adr12: FDCPE port map (turbo_rom_adr(12),turbo_rom_adr_D(12),NOT phi2,'0','0'); turbo_rom_adr_D(12) <= ((NOT turbo_rom_adr(12) AND NOT turbo_rom_adr_11__or0001/turbo_rom_adr_11__or0001_D2) OR (data(5).PIN AND reset AND turbo_rom_adr_11__or0001/turbo_rom_adr_11__or0001_D2)); turbo_rom_adr_11__or0001/turbo_rom_adr_11__or0001_D2 <= ((NOT reset) OR (adr(12) AND NOT d7_ram_rom.PIN AND NOT adr(11) AND check_1050_6810_access_cmp_eq0000/check_1050_6810_access_cmp_eq0000_D2)); turbo_speed_out <= ((floppy_mode(3) AND NOT floppy_mode(0) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND NOT riot_ready_inout.PIN) OR (NOT floppy_mode(3) AND floppy_mode(0) AND floppy_mode(2) AND NOT floppy_mode(1) AND turbo_speed_in)); Register Legend: FDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); ****************************** Device Pin Out ***************************** Device : XC95144XL-10-TQ100 -------------------------------------------------- /100 98 96 94 92 90 88 86 84 82 80 78 76 \ | 99 97 95 93 91 89 87 85 83 81 79 77 | | 1 75 | | 2 74 | | 3 73 | | 4 72 | | 5 71 | | 6 70 | | 7 69 | | 8 68 | | 9 67 | | 10 66 | | 11 65 | | 12 64 | | 13 XC95144XL-10-TQ100 63 | | 14 62 | | 15 61 | | 16 60 | | 17 59 | | 18 58 | | 19 57 | | 20 56 | | 21 55 | | 22 54 | | 23 53 | | 24 52 | | 25 51 | | 27 29 31 33 35 37 39 41 43 45 47 49 | \26 28 30 32 34 36 38 40 42 44 46 48 50 / -------------------------------------------------- Pin Signal Pin Signal No. Name No. Name 1 data<7> 51 VCC 2 ram_rom_adr<8> 52 cfg_enc_b 3 turbo_speed_out 53 cfg_enc_a 4 turbo_speed_in 54 cfg_enc_ok 5 VCC 55 cfg_sw1 6 data<6> 56 centronics_busy 7 riot_ready_in 57 VCC 8 data<5> 58 centronics_data 9 data<4> 59 centronics_strobe 10 data<3> 60 centronics_clk 11 data<2> 61 cfg_sw2 12 data<1> 62 GND 13 data<0> 63 i2c_data_pin 14 adr<0> 64 i2c_clk_pin 15 adr<1> 65 d7_ram_rom 16 adr<2> 66 io_1050 17 adr<3> 67 summer 18 adr<4> 68 density<2> 19 ram_rom_adr<9> 69 GND 20 adr<5> 70 density<1> 21 GND 71 density<0> 22 adr<11> 72 track_hi<6> 23 adr<12> 73 fdc_write_out 24 ram_rom_adr<10> 74 track_hi<5> 25 adr<6> 75 GND 26 VCC 76 track_hi<4> 27 phi2 77 track_hi<3> 28 adr<7> 78 track_hi<2> 29 adr<8> 79 track_hi<1> 30 adr<9> 80 cfg_led 31 GND 81 track_hi<0> 32 adr<10> 82 track_lo<6> 33 ram_rom_adr<11> 83 TDO 34 riot_ready_inout 84 GND 35 ram_rom_adr<12> 85 track_lo<5> 36 adr<13> 86 track_lo<4> 37 adr<14> 87 track_lo<3> 38 VCC 88 VCC 39 adr<15> 89 track_lo<2> 40 rw 90 track_lo<1> 41 rom_ce 91 track_lo<0> 42 ram_ce 92 ram_rom_adr<18> 43 archiver_a11 93 ram_rom_adr<17> 44 GND 94 ram_rom_adr<16> 45 TDI 95 ram_rom_adr<15> 46 fdc_write_in 96 ram_rom_adr<14> 47 TMS 97 ram_rom_adr<13> 48 TCK 98 VCC 49 ram_rom_oe 99 reset_in 50 ram_rom_we 100 GND Legend : NC = Not Connected, unbonded pin PGND = Unused I/O configured as additional Ground pin TIE = Unused I/O floating -- must tie to VCC, GND or other signal KPR = Unused I/O with weak keeper (leave unconnected) VCC = Dedicated Power Pin GND = Dedicated Ground Pin TDI = Test Data In, JTAG pin TDO = Test Data Out, JTAG pin TCK = Test Clock, JTAG pin TMS = Test Mode Select, JTAG pin PROHIBITED = User reserved pin **************************** Compiler Options **************************** Following is a list of all global compiler options used by the fitter run. Device(s) Specified : xc95144xl-10-TQ100 Optimization Method : DENSITY Multi-Level Logic Optimization : ON Ignore Timing Specifications : OFF Default Register Power Up Value : LOW Keep User Location Constraints : ON What-You-See-Is-What-You-Get : OFF Exhaustive Fitting : OFF Keep Unused Inputs : OFF Slew Rate : SLOW Power Mode : LOW Ground on Unused IOs : OFF Set I/O Pin Termination : KEEPER Global Clock Optimization : ON Global Set/Reset Optimization : ON Global Ouput Enable Optimization : ON Input Limit : 54 Pterm Limit : 90