Signal Name | Total Pterms | Total Inputs | Function Block | Macrocell | Power Mode | Slew Rate | Pin Number | Pin Type | Pin Use | Reg Init State | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|
data<7> | 12 | 28 | FB2 | MC5 | LOW | SLOW | 1 | I/O/GTS3 | I/O | ||||
ram_rom_adr<8> | 2 | 4 | FB2 | MC6 | LOW | SLOW | 2 | I/O/GTS4 | O | ||||
turbo_speed_out | 2 | 6 | FB2 | MC8 | LOW | SLOW | 3 | I/O/GTS1 | O | ||||
data<6> | 2 | 5 | FB2 | MC11 | LOW | SLOW | 6 | I/O | I/O | ||||
data<5> | 4 | 8 | FB2 | MC14 | LOW | SLOW | 8 | I/O | I/O | ||||
data<4> | 5 | 9 | FB2 | MC15 | LOW | SLOW | 9 | I/O | I/O | ||||
data<3> | 6 | 10 | FB2 | MC17 | LOW | SLOW | 10 | I/O | I/O | ||||
data<2> | 6 | 10 | FB1 | MC2 | LOW | SLOW | 11 | I/O | I/O | ||||
data<1> | 5 | 8 | FB1 | MC3 | LOW | SLOW | 12 | I/O | I/O | ||||
data<0> | 5 | 8 | FB1 | MC5 | LOW | SLOW | 13 | I/O | I/O | ||||
$OpTx$FX_SC$508 | 1 | 3 | FB1 | MC6 | LOW | 14 | I/O | I | |||||
rom_base_bank_0 | 2 | 4 | FB1 | MC8 | LOW | 15 | I/O | I | RESET | ||||
rom_bank_c000_enable<0> | 2 | 4 | FB1 | MC9 | LOW | 16 | I/O | I | RESET | ||||
rom_bank_c000_2 | 2 | 4 | FB1 | MC11 | LOW | 17 | I/O | I | RESET | ||||
rom_bank_c000_1 | 2 | 4 | FB1 | MC12 | LOW | 18 | I/O | I | RESET | ||||
ram_rom_adr<9> | 1 | 3 | FB1 | MC14 | LOW | SLOW | 19 | I/O | O | ||||
floppy_mode<3> | 2 | 4 | FB1 | MC15 | LOW | 20 | I/O | I | RESET | ||||
floppy_mode<1> | 2 | 4 | FB1 | MC17 | LOW | 22 | I/O/GCK1 | I | SET | ||||
turbo_rom_adr_11__or0001/turbo_rom_adr_11__or0001_D2 | 2 | 5 | FB3 | MC2 | LOW | 23 | I/O/GCK2 | I | |||||
ram_rom_adr<10> | 3 | 8 | FB3 | MC5 | LOW | SLOW | 24 | I/O | O | ||||
rom_base_bank_3 | 2 | 4 | FB3 | MC6 | LOW | 25 | I/O | I | SET | ||||
rom_bank_c000_5 | 2 | 4 | FB3 | MC8 | LOW | 27 | I/O/GCK3 | GCK/I | RESET | ||||
rom_bank_c000_4 | 2 | 4 | FB3 | MC9 | LOW | 28 | I/O | I | RESET | ||||
ram_bank_4 | 2 | 5 | FB3 | MC11 | LOW | 29 | I/O | I | RESET | ||||
ram_bank_3 | 2 | 5 | FB3 | MC12 | LOW | 30 | I/O | I | RESET | ||||
ram_bank_1 | 2 | 5 | FB3 | MC14 | LOW | 32 | I/O | I | RESET | ||||
ram_rom_adr<11> | 9 | 12 | FB3 | MC15 | LOW | SLOW | 33 | I/O | O | ||||
riot_ready_inout | 2 | 5 | FB3 | MC17 | LOW | SLOW | 34 | I/O | I/O | ||||
ram_rom_adr<12> | 22 | 17 | FB5 | MC2 | LOW | SLOW | 35 | I/O | O | ||||
data_0_cmp_eq0002/data_0_cmp_eq0002_D2 | 1 | 16 | FB5 | MC5 | LOW | 36 | I/O | I | |||||
turbo_centronics_clk__or0001/turbo_centronics_clk__or0001_D2 | 2 | 4 | FB5 | MC6 | LOW | 37 | I/O | I | |||||
data_0_or0000/data_0_or0000_D2 | 2 | 20 | FB5 | MC8 | LOW | 39 | I/O | I | |||||
$OpTx$FX_DC$475 | 2 | 4 | FB5 | MC9 | LOW | 40 | I/O | I | |||||
rom_ce | 9 | 12 | FB5 | MC11 | LOW | SLOW | 41 | I/O | O | ||||
ram_ce | 14 | 15 | FB5 | MC12 | LOW | SLOW | 42 | I/O | O | ||||
i2c_clk | 3 | 6 | FB5 | MC14 | LOW | 43 | I/O | I | SET | ||||
happy_a12 | 3 | 7 | FB5 | MC15 | LOW | 46 | I/O | I | RESET | ||||
ram_rom_oe | 1 | 2 | FB5 | MC17 | LOW | SLOW | 49 | I/O | O | ||||
ram_rom_we | 1 | 2 | FB7 | MC2 | LOW | SLOW | 50 | I/O | O | ||||
reset_sync | 1 | 1 | FB7 | MC6 | LOW | 53 | I/O | I | RESET | ||||
N104/N104_D2 | 1 | 4 | FB7 | MC8 | LOW | 54 | I/O | I | |||||
$OpTx$FX_DC$501 | 1 | 2 | FB7 | MC9 | LOW | 55 | I/O | I | |||||
turbo_rom_adr<11> | 2 | 5 | FB7 | MC11 | LOW | 56 | I/O | I | SET | ||||
centronics_data | 3 | 5 | FB7 | MC12 | LOW | SLOW | 58 | I/O | O | SET | |||
centronics_strobe | 2 | 5 | FB7 | MC14 | LOW | SLOW | 59 | I/O | O | SET | |||
centronics_clk | 3 | 5 | FB7 | MC15 | LOW | SLOW | 60 | I/O | O | SET | |||
rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2 | 2 | 3 | FB7 | MC17 | LOW | 61 | I/O | I | |||||
i2c_data_pin | 1 | 1 | FB8 | MC2 | LOW | SLOW | 63 | I/O | I/O | ||||
i2c_clk_pin | 1 | 1 | FB8 | MC5 | LOW | SLOW | 64 | I/O | O | ||||
d7_ram_rom | 2 | 4 | FB8 | MC6 | LOW | SLOW | 65 | I/O | I/O | ||||
io_1050 | 7 | 10 | FB8 | MC8 | LOW | SLOW | 66 | I/O | O | ||||
summer | 2 | 11 | FB8 | MC9 | LOW | SLOW | 67 | I/O | O | RESET | |||
density<2> | 4 | 15 | FB8 | MC11 | LOW | SLOW | 68 | I/O | O | RESET | |||
density<1> | 4 | 15 | FB8 | MC12 | LOW | SLOW | 70 | I/O | O | RESET | |||
density<0> | 5 | 16 | FB8 | MC14 | LOW | SLOW | 71 | I/O | O | RESET | |||
track_hi<6> | 4 | 15 | FB8 | MC15 | LOW | SLOW | 72 | I/O | O | RESET | |||
fdc_write_out | 2 | 3 | FB8 | MC17 | LOW | SLOW | 73 | I/O | O | ||||
track_hi<5> | 5 | 15 | FB6 | MC2 | LOW | SLOW | 74 | I/O | O | RESET | |||
track_hi<4> | 4 | 14 | FB6 | MC5 | LOW | SLOW | 76 | I/O | O | RESET | |||
track_hi<3> | 4 | 16 | FB6 | MC6 | LOW | SLOW | 77 | I/O | O | RESET | |||
track_hi<2> | 4 | 16 | FB6 | MC8 | LOW | SLOW | 78 | I/O | O | RESET | |||
track_hi<1> | 3 | 11 | FB6 | MC9 | LOW | SLOW | 79 | I/O | O | RESET | |||
cfg_led | 2 | 4 | FB6 | MC11 | LOW | SLOW | 80 | I/O | O | RESET | |||
track_hi<0> | 4 | 16 | FB6 | MC12 | LOW | SLOW | 81 | I/O | O | RESET | |||
track_lo<6> | 6 | 18 | FB6 | MC14 | LOW | SLOW | 82 | I/O | O | RESET | |||
track_lo<5> | 7 | 18 | FB6 | MC15 | LOW | SLOW | 85 | I/O | O | RESET | |||
track_lo<4> | 6 | 18 | FB6 | MC17 | LOW | SLOW | 86 | I/O | O | RESET | |||
track_lo<3> | 7 | 17 | FB4 | MC2 | LOW | SLOW | 87 | I/O | O | RESET | |||
track_lo<2> | 6 | 17 | FB4 | MC5 | LOW | SLOW | 89 | I/O | O | RESET | |||
track_lo<1> | 7 | 17 | FB4 | MC6 | LOW | SLOW | 90 | I/O | O | RESET | |||
track_lo<0> | 7 | 17 | FB4 | MC8 | LOW | SLOW | 91 | I/O | O | RESET | |||
ram_rom_adr<18> | 5 | 14 | FB4 | MC9 | LOW | SLOW | 92 | I/O | O | ||||
ram_rom_adr<17> | 4 | 12 | FB4 | MC11 | LOW | SLOW | 93 | I/O | O | ||||
ram_rom_adr<16> | 4 | 12 | FB4 | MC12 | LOW | SLOW | 94 | I/O | O | ||||
ram_rom_adr<15> | 4 | 13 | FB4 | MC14 | LOW | SLOW | 95 | I/O | O | ||||
ram_rom_adr<14> | 10 | 12 | FB4 | MC15 | LOW | SLOW | 96 | I/O | O | ||||
ram_rom_adr<13> | 9 | 18 | FB4 | MC17 | LOW | SLOW | 97 | I/O | O | ||||
riot_ready_in_IBUF$BUF0/riot_ready_in_IBUF$BUF0_TRST | 1 | 4 | FB1 | MC1 | LOW | (b) | (b) | ||||||
check_1050_6810_access_cmp_eq0000/check_1050_6810_access_cmp_eq0000_D2 | 1 | 4 | FB1 | MC4 | LOW | (b) | (b) | ||||||
rom_base_bank_1 | 2 | 4 | FB1 | MC7 | LOW | (b) | (b) | D | RESET | ||||
rom_bank_c000_3 | 2 | 4 | FB1 | MC10 | LOW | (b) | (b) | D | RESET | ||||
rom_bank_c000_0 | 2 | 4 | FB1 | MC13 | LOW | (b) | (b) | D | RESET | ||||
floppy_mode<2> | 2 | 4 | FB1 | MC16 | LOW | (b) | (b) | D | RESET | ||||
floppy_mode<0> | 2 | 4 | FB1 | MC18 | LOW | (b) | (b) | D | SET | ||||
rom_base_bank_5 | 2 | 4 | FB3 | MC3 | LOW | (b) | (b) | D | SET | ||||
rom_base_bank_4 | 2 | 4 | FB3 | MC4 | LOW | (b) | (b) | D | SET | ||||
rom_base_bank_2 | 2 | 4 | FB3 | MC7 | LOW | (b) | (b) | D | RESET | ||||
rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2 | 2 | 4 | FB3 | MC10 | LOW | (b) | (b) | ||||||
ram_bank_2 | 2 | 5 | FB3 | MC13 | LOW | (b) | (b) | D | RESET | ||||
ram_bank_0 | 2 | 5 | FB3 | MC16 | LOW | (b) | (b) | D | RESET | ||||
i2c_data | 3 | 6 | FB3 | MC18 | LOW | (b) | (b) | T | SET | ||||
i2c_clk_and0000/i2c_clk_and0000_D2 | 1 | 14 | FB5 | MC4 | LOW | (b) | (b) | ||||||
ram_bank_5 | 2 | 10 | FB5 | MC7 | LOW | (b) | (b) | D | RESET | ||||
$OpTx$FX_DC$461 | 2 | 5 | FB5 | MC10 | LOW | (b) | (b) | ||||||
data_7_or0005/data_7_or0005_D2 | 5 | 22 | FB5 | MC16 | LOW | (b) | (b) | ||||||
$OpTx$FX_DC$556 | 5 | 12 | FB5 | MC18 | LOW | (b) | (b) | ||||||
$OpTx$FX_DC$515 | 1 | 7 | FB6 | MC1 | LOW | (b) | (b) | ||||||
happy_a12__or0001/happy_a12__or0001_D2 | 2 | 15 | FB6 | MC3 | LOW | (b) | (b) | ||||||
N64/N64_D2 | 2 | 7 | FB6 | MC4 | LOW | (b) | (b) | ||||||
$OpTx$FX_SC$520 | 2 | 11 | FB6 | MC7 | LOW | (b) | (b) | ||||||
$OpTx$FX_DC$531 | 2 | 7 | FB6 | MC10 | LOW | (b) | (b) | ||||||
$OpTx$FX_DC$492 | 3 | 10 | FB6 | MC13 | LOW | (b) | (b) | ||||||
check_1050_6810_access_mux0001/check_1050_6810_access_mux0001_D2 | 5 | 8 | FB6 | MC16 | LOW | (b) | (b) | ||||||
$OpTx$FX_DC$554 | 8 | 14 | FB6 | MC18 | LOW | (b) | (b) | ||||||
reset | 1 | 1 | FB7 | MC7 | LOW | (b) | (b) | D | RESET | ||||
turbo_rom_adr<12> | 2 | 4 | FB7 | MC10 | LOW | (b) | (b) | D | SET | ||||
rom_source_is_ram | 2 | 4 | FB7 | MC13 | LOW | (b) | (b) | D | RESET | ||||
rom_base_bank_6 | 2 | 4 | FB7 | MC16 | LOW | (b) | (b) | D | SET | ||||
$OpTx$FX_DC$517 | 2 | 4 | FB7 | MC18 | LOW | (b) | (b) | ||||||
data_0_cmp_eq0001/data_0_cmp_eq0001_D2 | 1 | 16 | FB8 | MC1 | LOW | (b) | (b) | ||||||
data_0_cmp_eq0000/data_0_cmp_eq0000_D2 | 1 | 16 | FB8 | MC3 | LOW | (b) | (b) | ||||||
$OpTx$FX_DC$529 | 1 | 17 | FB8 | MC4 | LOW | (b) | (b) | ||||||
floppy_mode_0__or0000/floppy_mode_0__or0000_D2 | 2 | 18 | FB8 | MC7 | LOW | (b) | (b) | ||||||
N27/N27_D2 | 3 | 9 | FB8 | MC10 | LOW | (b) | (b) | ||||||
N2/N2_D2 | 3 | 10 | FB8 | MC13 | LOW | (b) | (b) | ||||||
N11/N11_D2 | 3 | 10 | FB8 | MC16 | LOW | (b) | (b) | ||||||
$OpTx$FX_DC$502 | 3 | 10 | FB8 | MC18 | LOW | (b) | (b) |